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Improving data locality with loop transformations
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Source ACM Transactions on Programming Languages and Systems (TOPLAS) archive
Volume 18 ,  Issue 4  (July 1996) table of contents
Pages: 424 - 453  
Year of Publication: 1996
ISSN:0164-0925
Authors
Kathryn S. McKinley  Computer Science Department, LGRC, University of Massachusetts, Amherst, MA
Steve Carr  Department of Computer Science, Michigan Technological University, Houghton, MI
Chau-Wen Tseng  Department of Computer Science, University of Maryland, College Park, MD
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 25,   Downloads (12 Months): 174,   Citation Count: 129
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ABSTRACT

In the past decade, processor speed has become significantly faster than memory speed. Small, fast cache memories are designed to overcome this discrepancy, but they are only effective when programs exhibit data locality. In the this article, we present compiler optimizations to improve data locality based on a simple yet accurate cost model. The model computes both temporal and spatial reuse of cache lines to find desirable loop organizations. The cost model drives the application of compound transformations consisting of loop permutation, loop fusion, loop distribution, and loop reversal. To validate our optimization strategy, we implemented our algorithms and ran experiments on a large collection of scientific programs and kernels. Experiments illustrate that for kernels our model and algorithm can select and achieve the best loop structure for a nest. For over 30 complete applications, we executed the original and transformed versions and simulated cache hit rates. We collected statistics about the inherent characteristics of these programs and our ability to improve their data locality. To our knowledge, these studies are the first of such breadth and depth. We found performance improvements were difficult to achieve bacause benchmark programs typically have high hit rates even for small data caches; however, our optimizations significanty improved several programs.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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CARR, S. AND WU, Q. 1995. An analysis of loop permutation on the HP PA-RISC. Tech. Rep. TR95-03, Michigan Technological Univ., Houghton, Mich. Feb.
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COOPER, K., HALL, M. W., HOOD, R. T., KENNEDY, K., MCKINLEY, K. S., MELLOR-CRUMMEY, J. M., TORCZON, L., AND WARREN, S. K. 1993. The ParaScope parallel programming environmerit. Proc. IEEE 81, 2 (Feb.), 244-263.
 
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KENNEDY, K., MCKINLEY, K. S., AND TSENG, C.-W. 1993. Analysis and transformation in an interactive parallel programming tool. Concurrency Pract. Exper. 5, 7 (Oct.), 575-602.
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CITED BY  130


REVIEW

"Noah S. Prywes : Reviewer"

When using a processor with a cache memory of limited size, the order of memory referencing in the program can affect the overall computation time. It would be too difficult for a programmer to consider this effect in composing a program. Inst  more...

Collaborative Colleagues:
Kathryn S. McKinley: colleagues
Steve Carr: colleagues
Chau-Wen Tseng: colleagues