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Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches
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Source International Symposium on Computer Architecture archive
Proceedings of the 23rd annual international symposium on Computer architecture table of contents
Philadelphia, Pennsylvania, United States
Pages: 3 - 11  
Year of Publication: 1996
ISBN:0-89791-786-3
Also published in ...
Authors
Marius Evers  Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
Po-Yung Chang  Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
Yale N. Patt  Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
Sponsors
IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 14,   Downloads (12 Months): 67,   Citation Count: 27
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ABSTRACT

Pipeline stalls due to conditional branches represent one of the most significant impediments to realizing the performance potential of deeply pipelined, superscalar processors. Many branch predictors have been proposed to help alleviate this problem, including the Two-Level Adaptive Branch Predictor, and more recently, two-component hybrid branch predictors.In a less idealized environment, such as a time-shared system, code of interest involves context switches. Context switches, even at fairly large intervals, can seriously degrade the performance of many of the most accurate branch prediction schemes. In this paper, we introduce a new hybrid branch predictor and show that it is more accurate (for a given cost) than any previously published scheme, especially if the branch histories are periodically flushed due to the presence of context switches.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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P. Chang and U. Banerjee, "Profile-guided Multiheuristic Branch Prediction", Proceedings of the International Conference on Parallel Processing, July, 1995.
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J.K.F. Lee and A.j. Smith, "Branch Prediction StrategiesBranch Target Buffer Design," IEEE Computer, pp.6-22, January 1984.
 
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S. McFarling, "Combining Branch Predictors", WRL Technical Note TN-36_Digital Equipment Corporation, June 1993.
 
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The PowerPC Architecture: A Specification for a New Family of RISC Processors, Ed. C. May et al, Morgan Kaufmann Publishers, Inc., San Francisco, CA, 1994.
 
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CITED BY  27

Collaborative Colleagues:
Marius Evers: colleagues
Po-Yung Chang: colleagues
Yale N. Patt: colleagues