Emerald

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Emerald: an architecture-driven tool compiler for FPGAs

Full text

Pdf (212 KB)

Source

International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays table of contents

Monterey, California, United States

Pages: 144 - 150

Year of Publication: 1996

ISBN:0-89791-773-1

Authors

Darren C. Cronquist	Department of Computer Science and Engineering, University of Washington, Box 352350, Seattle, WA
Larry McMurchie	Department of Computer Science and Engineering, University of Washington, Box 352350, Seattle, WA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 12, Citation Count: 1

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/228370.228391 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Larry McMurchie , Carl Ebeling, PathFinder: a negotiation-based performance-driven router for FPGAs, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.111-117, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201328]
	2	Kalapi Roy, A timing-driven multi-way partitioning system for integrated circuits and multi-chip systems, University of Washington, Seattle, WA, 1994
	3	K. Roy, B. Guan, and C. Sechen, ;;A sea-of-gate style FPGA placement algorithm," in Proceedings of Seventh IEEE International Conference VLSI Design, Calcutta, India, pp. 221-224, January 1994.
	4	E. Sentovich et al., ;;SIS: A System for Sequential Circuit Synthesis," Electronics Research Laboratory Memorandum No. UCB/ERL M92/41, Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, CA, May 1992.
	5	L. Trevillyan, ;;An Experiment in Technology Mapping for FPGAs using a Fixed Library," IWLS Workshop Notes, pp. P9cl-P9cT, 1993.
	6	Dwight D. Hill, A CAD system for the design of field programmable gate arrays, Proceedings of the 28th conference on ACM/IEEE design automation, p.187-192, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127662]
	7	Atmel Corp., ;;AT6000 Series Field Programmable Gate Arrays", August 1993.
	8	Gatefield (a division of Zycad Corp.), ;;GF100K series DATAbook", 1994.