RASP

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

RASP: a general logic synthesis system for SRAM-based FPGAs

Full text

Pdf (192 KB)

Source

International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays table of contents

Monterey, California, United States

Pages: 137 - 143

Year of Publication: 1996

ISBN:0-89791-773-1

Authors

Jason Cong	Department of Computer Science, University of California, Los Angeles, CA
John Peck	Department of Computer Science, University of California, Los Angeles, CA
Yuzheng Ding	AT&T Bell Laboratories, Murray Hill, NJ

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 18, Citation Count: 29

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/228370.228390 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	Al95	Altera, Flex 8000 and Flex 10000 Programmable Logic Device Family Data Sheets. San Jose, CA: Altera 1995.
	AT&T95	AT&T Microelectronics, Optimized Reconfi'gurable Cell Array (ORCA) Series FPGAs. Allentown, PA: AT&T Microelectronics 1995.
	ChCD92	Kuang-Chien Chen , Jason Cong , Yuzheng Ding , Andrew B. Kahng , Peter Trajmar, DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization, IEEE Design & Test, v.9 n.3, p.7-20, July 1992 [doi>10.1109/54.156154]
	CoDi92a	Jason Cong , Yuzheng Ding, An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.48-53, November 1992, Santa Clara, California, United States
	CoDi93b	Jason Cong , Yuzheng Ding, Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.110-114, November 07-11, 1993, Santa Clara, California, United States
	CoDi94a	Cong, J. and Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs," IEEE Trans. on Computer-Aided Design, Vol. 13(1) pp. 1-12, 1994.
	CoDi94b	Cong, J. and Y. Ding, "On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping," IEEE Trans. on VLSI Systems, Vol. 2, June 1994.
	CoHw95a	Jason Cong , Yean-Yow Hwang, Simultaneous depth and area minimization in LUT-based FPGA mapping, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.68-74, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201322]
	FrRC90	Robert J. Francis , Jonathan Rose , Kevin Chung, Chortle: a technology mapping program for lookup table-based field programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.613-619, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123418]
	FrRV91b	Francis, R. J., J. Rose, and Z. Vranesic, "Technology Mapping for Delay Optimization of Lookup Table- Based FPGAs," MCNC Logic Synthesis Workshop, 1991.
	Ka91a	Kevin Karplus, Xmap: A technology mapper for table-lookup field-programmable gate arrays, Proceedings of the 28th conference on ACM/IEEE design automation, p.240-243, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127672]
	LaPV93	Yung-Te Lai , Massoud Pedram , Sarma B. K. Vrudhula, BDD based decomposition of logic functions with application to FPGA synthesis, Proceedings of the 30th international conference on Design automation, p.642-647, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165078]
	MuNS90	Rajeev Murgai , Yoshihito Nishizaki , Narendra Shenoy , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Logic synthesis for programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.620-625, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123421]
	MuSB91a	Murgai, R., N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Improved Logic Synthesis Algorithms for Table Look Up Architectures," Proc. IEEE Int'l Conf. on Computer-Aided Design, pp. 564- 567, Santa Clara, CA, Nov. 1991.
	MuSB91b	Murgai, R., Y. Nishizaki, N. Shenoy, R. Brayton, and A. Sangiovanni-Vincentelli, "Performance Directed Synthesis for Table Look Up Programmable Gate Arrays," Proc. IEEE Intl'l Conf. on Computer-Aided Design, pp. 572-575, Nov. 1991.
	SaTh92	Sawkar, P., D. Thomas, "Technology Mapping for Table-Look-Up Based Field Programmable Gate Arrays," ACM/SIGDA Workshop on Field Programmable Gate Arrays, pp. 82-88, Feb. 1992.
	ScKC92	Martine D. F. Schlag , Jackson Kong , Pak K. Chan, Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.86-90, October 11-14, 1992
	ScVMJ95	Brian Schoner , John Villasenor , Steve Molloy , Rajeev Jain, Techniques for FPGA implementation of video compression systems, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.154-159, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201334]
	SeSL92	Sentovich, E., K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephen, R. Brayton, and A. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis," U.C. Berkeley Technical Report UCB/ERL M92/41, May, 1992.
	Xi94a	Xilinx, The Programmable Logic Data Book. San Jose, CA: Xilinx 1994.
	Wo91a	Nam-Sung Woo, A heuristic method for FPGA technology mapping based on the edge visibility, Proceedings of the 28th conference on ACM/IEEE design automation, p.248-251, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127675]

CITED BY 29

	Jason Cong , Yuzheng Ding, Combinational logic synthesis for LUT based field programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.145-204, April 1996
	Jason Cong , Yizhou Lin , Wangning Long, SPFD-based global rewiring, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
	Jason Cong , Michail Romesis, Performance-driven multi-level clustering with application to hierarchical FPGA mapping, Proceedings of the 38th conference on Design automation, p.389-394, June 2001, Las Vegas, Nevada, United States
	Jason Cong , Songjie Xu, Technology mapping for FPGAs with embedded memory blocks, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.179-188, February 22-25, 1998, Monterey, California, United States
	Gang Chen , Jason Cong, Simultaneous logic decomposition with technology mapping in FPGA designs, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.48-55, February 2001, Monterey, California, United States
	Jason Cong , Yean-Yow Hwang, Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design, Proceedings of the 33rd annual conference on Design automation, p.726-729, June 03-07, 1996, Las Vegas, Nevada, United States
	Jason Cong , Hui Huang , Xin Yuan, Technology mapping for k/m-macrocell based FPGAs, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.51-59, February 10-11, 2000, Monterey, California, United States
	Jason Cong , Yean-Yow Hwang, Partially-dependent functional decomposition with applications in FPGA synthesis and mapping, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.35-42, February 09-11, 1997, Monterey, California, United States
	Jason Cong , Yean-Yow Hwang, Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.193-225, April 2000
	Jason Cong , Kenneth Yan, Synthesis for FPGAs with embedded memory blocks, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.75-82, February 10-11, 2000, Monterey, California, United States
	Jason Cong , Joey Y. Lin , Wangning Long, A new enhanced SPFD rewiring algorithm, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.672-678, November 10-14, 2002, San Jose, California
	Fei Li , Yan Lin , Lei He , Jason Cong, Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Jason Cong , Yean-Yow Hwang, Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.27-34, February 22-25, 1998, Monterey, California, United States
	Jason Cong , Chang Wu, FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits, Proceedings of the 34th annual conference on Design automation, p.644-649, June 09-13, 1997, Anaheim, California, United States
	Fei Li , Deming Chen , Lei He , Jason Cong, Architecture evaluation for power-efficient FPGAs, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Jason Cong , Songjie Xu, Delay-optimal technology mapping for FPGAs with heterogeneous LUTs, Proceedings of the 35th annual conference on Design automation, p.704-707, June 15-19, 1998, San Francisco, California, United States
	Navin Vemuri , Priyank Kalla , Russell Tessier, BDD-based logic synthesis for LUT-based FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.4, p.501-525, October 2002
	Jason Cong , Hui Huang , Xin Yuan, Technology mapping and architecture evalution for k/m-macrocell-based FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.3-23, January 2005
	Andrew Ling , Deshanand P. Singh , Stephen D. Brown, FPGA technology mapping: a study of optimality, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Chang Woo Kang , Massoud Pedram, Clustering techniques for coarse-grained, antifuse FPGAs, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Jason Cong , Kirill Minkovich, Optimality study of logic synthesis for LUT-based FPGAs, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Chang Woo Kang , Massoud Pedram, Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Ian Kuon , Jonathan Rose, Area and delay trade-offs in the circuit and architecture design of FPGAs, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	Jason Cong , Kirill Minkovich, Improved SAT-based Boolean matching using implicants for LUT-based FPGAs, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, February 18-20, 2007, Monterey, California, USA
	Jason Meyer , Fatih Kocan, Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.2, p.182-195, February 2007
	Stephen Bijansky , Adnan Aziz, TuneFPGA: post-silicon tuning of dual-Vdd FPGAs, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Kirill Minkovich , Jason Cong, Mapping for better than worst-case delays in LUT-based FPGA designs, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	Robert P. McEvoy , Colin C. Murphy , William P. Marnane , Michael Tunstall, Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs, ACM Transactions on Reconfigurable Technology and Systems (TRETS), v.2 n.1, p.1-23, March 2009
	Ion Bucur , Ioana Fagarasan , Cornel Popescu , Costin-Anton Boiangiu , George Culea, On K-LUT based FPGA optimum delay and optimal area mapping, Proceedings of the 10th WSEAS international conference on Mathematical and computational methods in science and engineering, p.137-142, November 07-09, 2008, Bucharest, Romania