Sequencing run-time reconfigured hardware with software

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Sequencing run-time reconfigured hardware with software

Full text

Pdf (220 KB)

Source

International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays table of contents

Monterey, California, United States

Pages: 122 - 128

Year of Publication: 1996

ISBN:0-89791-773-1

Authors

Michael J. Wirthlin	Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT
Brad L. Hutchings	Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 20, Citation Count: 13

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/228370.228388 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. Trimberger. A reprogrammable gate array and applications. Proceedings of the IEEE, pages 1030-1041, July 1993.
	2	Patrice Bertin , Didier Roncin , Jean Vuillemin, Programmable active memories: a performance assessment, Proceeding of the 1993 symposium on Research on integrated systems, p.88-102, February 1993, Seattle, Washington, United States
	3	Brad Hutchings , Michael J. Wirthlin, Implementation Approaches for Reconfigurable Logic Applications, Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications, p.419-428, September 01, 1995
	4	J. G. Eldredge and B. L. HHutchings. Density enhancement of a neural network using FPGAs and run-time reconfiguration. In D. A. Buell and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 180-188, Napa, CA, April 1994.
	5	J. D. Hadley, Design methodologies for partially reconfigured systems, Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines, p.78, April 19-21, 1995
	6	B. Schoner , C. Jones , J. Villasenor, Issues in wireless video coding using run-time-reconfigurable FPGAs, Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines, p.85, April 19-21, 1995
	7	National Semiconductor. Configurable Logic Array (CLAy) Data Sheet, December 1993.
	8	C. R. Rupp. CLAyFUNtm Reference Manual. National Semiconductor, September 1994. Version 2.00.
	9	D. A. Clark. DASM Reference Manual. Brigham Young University, Provo, Utah, 1995.
	10	Christopher W. Fraser , David R. Hanson, A Retargetable C Compiler: Design and Implementation, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1995
	11	J. R. Parker, Practical computer vision using C, John Wiley & Sons, Inc., New York, NY, 1993
	12	T. Y. Zhang , C. Y. Suen, A fast parallel algorithm for thinning digital patterns, Communications of the ACM, v.27 n.3, p.236-239, March 1984 [doi>10.1145/357994.358023]

CITED BY 13

	Meenakshi Kaul , Ranga Vemuri , Sriram Govindarajan , Iyad Ouaiss, An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.616-622, June 21-25, 1999, New Orleans, Louisiana, United States
	Scott Hauck, Configuration prefetch for single context reconfigurable coprocessors, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.65-74, February 22-25, 1998, Monterey, California, United States
	Zhiyuan Li , Scott Hauck, Don't Care discovery for FPGA configuration compression, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.91-98, February 21-23, 1999, Monterey, California, United States
	Daler N. Rakhmatov , Sarma B. K. Vrudhula , Thomas J. Brown , Ajay Nagarandal, Adaptive Multiuser Online Reconfigurable Engine, IEEE Design & Test, v.17 n.1, p.53-67, January 2000
	A. C. Zawada , N. L. Seed , P. A. Ivey, Continuous and high coverage self-testing of dynamically re-configurable systems, Parallel Computing, v.28 n.7-8, p.1155-1178, August 2002
	Jack S. N. Jean , Karen Tomko , Vikram Yavagal , Jignesh Shah , Robert Cook, Dynamic Reconfiguration to Support Concurrent Applications, IEEE Transactions on Computers, v.48 n.6, p.591-602, June 1999
	Katherine Compton , Scott Hauck, Reconfigurable computing: a survey of systems and software, ACM Computing Surveys (CSUR), v.34 n.2, p.171-210, June 2002
	Dean R. D’Mello , P. Glenn Gulak, Design Approaches to Field-Programmable Analog Integrated Circuits, Analog Integrated Circuits and Signal Processing, v.17 n.1-2, p.7-34, Sept. 1998
	Esam El-Araby , Ivan Gonzalez , Tarek El-Ghazawi, Performance bounds of partial run-time reconfiguration in high-performance reconfigurable computing, Proceedings of the 1st international workshop on High-performance reconfigurable computing technology and applications: held in conjunction with SC07, November 11-11, 2007, Reno, Nevada
	Herman H. Schmit , Srihari Cadambi , Matthew Moe , Seth C. Goldstein, Pipeline Reconfigurable FPGAs, Journal of VLSI Signal Processing Systems, v.24 n.2-3, p.129-146, Mar. 2000
	Meenakshi Kaul , Ranga Vemuri, Design-Space Exploration for Block-Processing Based TemporalPartitioning of Run-Time Reconfigurable Systems, Journal of VLSI Signal Processing Systems, v.24 n.2-3, p.181-209, Mar. 2000
	Jack Jean , Xuejun Liang , Brian Drozd , Karen Tomko , Yan Wang, Automatic Target Recognition with Dynamic Reconfiguration, Journal of VLSI Signal Processing Systems, v.25 n.1, p.39-53, May 2000
	Meenakshi Kaul , Ranga Vemuri, Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs, Proceedings of the conference on Design, automation and test in Europe, p.43-es, January 1999, Munich, Germany