DPGA utilization and application

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DPGA utilization and application

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays table of contents

Monterey, California, United States

Pages: 115 - 121

Year of Publication: 1996

ISBN:0-89791-773-1

Author

André DeHon

MIT Artificial Intelligence Laboratory, NE43-791, 545 Technology Sq., Cambridge, MA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 19, Citation Count: 17

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Peter M. Athanas , Harvey F. Silverman, Processor reconfiguration through instruction-set metamorphosis, Computer, v.26 n.3, p.11-18, March 1993 [doi>10.1109/2.204677]
	2	Narasimha B. Bhat, Novel Techniques for High Performance Field, University of California at Berkeley, Berkeley, CA, 1993
	3	Andr~ DeHon. DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, 1994.
	4	Srinivas Devadas, Hi-Keung Ma,, A.R. Newton, and Alberto Sangiovanni-Vincentelli. MUSTANG: State Assignment of Finite State Machines Targeting Multilevel Logic Implementations. IEEE Transactions on Computer-Aided Design of lntegrated Circuits and Systems, 7(12):1290-1300, December 1988.
	5	Robert Francis. Technology Mapping for Lookup-Table Based Field-Programmable Gate Arrays. PhD thesis, University of Toronto, 1992.
	6	David Hawley. Advanced PLD Architectures. In Will Moore and Wayne Luk, editors, FPGAs, pages 11-23. Abingdon EE&CS Books, 15 Harcourt Way, Abingdon, OX14 1NV, UK, 1991.
	7	B. Schoner , C. Jones , J. Villasenor, Issues in wireless video coding using run-time-reconfigurable FPGAs, Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines, p.85, April 19-21, 1995
	8	Rahul Razdan, PRISC: programmable reduced instruction set computers, Harvard University, Cambridge, MA, 1994
	9	R. Rudell and A. Sangiovanni-Vincentelli. Multiple-Valued Minimization for PLA Optimization. IEEE Transactions on Computer-AidedDesign of lntegrated Circuits, 6(5):727-751, September 1987.
	10	Ellen M. Sentovich, Kanwar Jit Singh, Luciano Lavagno, Cho Moon, Rajeev Murgai, Alexander Saldanha, Hamid Savoj, Paul R. Stephan, Robert K. Brayton, and Alberto Sangiovanni- Vincentelli. SIS: A System for Sequential Circuit Synthesis. UCB/ERL M92/41, University of California, Berkeley, May 1992.
	11	Edward Tau, Ian Eslick, Derrick Chen, Jeremy Brown, and Andr6 DeHon. A First Generation DPGA Implementation. In Proceedings of the Third Canadian Workshop on Field- Programmable Devices, pages 138-143, May 1995.
	12	M. J. Wirthlin, A dynamic instruction set computer, Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines, p.99, April 19-21, 1995
	13	Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. The Programmable Logic Data Book, 1989, 1994.

CITED BY 17

	Douglas Chang , Malgorzata Marek-Sadowska, Partitioning sequential circuits on dynamically reconfiguable FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.161-167, February 22-25, 1998, Monterey, California, United States
	Ken Mai , Tim Paaske , Nuwan Jayasena , Ron Ho , William J. Dally , Mark Horowitz, Smart Memories: a modular reconfigurable architecture, ACM SIGARCH Computer Architecture News, v.28 n.2, p.161-171, May 2000
	Jerry Bauer , Michael Bershteyn , Ian Kaplan , Paul Vyedin, A reconfigurable logic machine for fast event-driven simulation, Proceedings of the 35th annual conference on Design automation, p.668-671, June 15-19, 1998, San Francisco, California, United States
	William Tsu , Kip Macy , Atul Joshi , Randy Huang , Norman Walker , Tony Tung , Omid Rowhani , Varghese George , John Wawrzynek , André DeHon, HSRA: high-speed, hierarchical synchronous reconfigurable array, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.125-134, February 21-23, 1999, Monterey, California, United States
	Mark Oskin , Frederic T. Chong , Timothy Sherwood, Active pages: a computation model for intelligent memory, ACM SIGARCH Computer Architecture News, v.26 n.3, p.192-203, June 1998
	S. R. Park , W. Burleson, Configuration cloning: exploiting regularity in dynamic DSP architectures, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.81-89, February 21-23, 1999, Monterey, California, United States
	Douglas Chang , Malgorzata Marek-Sadowska, Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.142-148, February 09-11, 1997, Monterey, California, United States
	Katherine Compton , Zhiyuan Li , James Cooley , Stephen Knol , Scott Hauck, Configuration relocation and defragmentation for run-time reconfigurable computing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.209-220, June 2002
	R. Kastner , A. Kaplan , S. Ogrenci Memik , E. Bozorgzadeh, Instruction generation for hybrid reconfigurable systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.4, p.605-627, October 2002
	Mahmoud Meribout , Masato Motomura, A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems, IEEE Transactions on Computers, v.53 n.12, p.1508-1522, December 2004
	Andre DeHon , Michael J. Wilson, Nanowire-based sublithographic programmable logic arrays, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Mahmoud Meribout , Masato Motomura, New design methodology with efficient prediction of quality metrics for logic level design towards dynamic reconfigurable logic, Journal of Systems Architecture: the EUROMICRO Journal, v.48 n.8-10, p.285-310, March 2003
	Douglas Chang , Malgorzata Marek-Sadowska, Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs, IEEE Transactions on Computers, v.48 n.6, p.565-578, June 1999
	Mahmoud Meribout , Masato Motomura, Efficient metrics and high-level synthesis for dynamically reconfigurable logic, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.6, p.603-621, June 2004
	Karthikeya M. Gajjala Purna , Dinesh Bhatia, Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers, IEEE Transactions on Computers, v.48 n.6, p.579-590, June 1999
	Katherine Compton , Scott Hauck, Reconfigurable computing: a survey of systems and software, ACM Computing Surveys (CSUR), v.34 n.2, p.171-210, June 2002
	Philip Garcia , Katherine Compton , Michael Schulte , Emily Blem , Wenyin Fu, An overview of reconfigurable hardware in embedded systems, EURASIP Journal on Embedded Systems, v.2006 n.1, p.13-13, January 2006