Evaluation of FPGA resources for built-in self-test of programmable logic blocks

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Evaluation of FPGA resources for built-in self-test of programmable logic blocks

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays table of contents

Monterey, California, United States

Pages: 107 - 113

Year of Publication: 1996

ISBN:0-89791-773-1

Authors

Charles Stroud	Dept. of Electrical Engineering, University of Kentucky
Ping Chen	Dept. of Electrical Engineering, University of Kentucky
Srinivasa Konala	Dept. of Electrical Engineering, University of Kentucky
Miron Abramovici	AT&T Bell Laboratories, Murray Hill, NJ

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 9

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Bradly K. Fawcett, Applications of reconfigurable logic, Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs, p.57-69, July 1994, Oxford, United Kingdom
	2	B. New, "Boundary-Scan Emulator for XC3000," XAPP Applications Handbook, Xilinx, Oct. 1992.
	3	A. Russ and C. Stroud, "Non-Intrusive Built-In Self-Test for Field Programmable Gate Array and Multi-Chip Module Applications", to be published in Proc. IEEE Automatic Test Conf., 1995.
	4	E. J. McCluskey, "Verification Testing - A Pseudoexhaustive Test Technique," IEEE Trans. on Computers, Vol. C-33, No. 6, pp. 541-546, June, 1984.
	5	Optimized Reconfigurable Cell Array (ORCA) 1C Series Field-Programmable Gate Arrays, Data Sheet, AT&T Microelectronics, May 1994.
	6	The Programmable Logic Data Book, Xilinx, Inc., 1993.
	7	Flex 8000 Programmable Logic Device Family, Data Sheet, Altera Corp., May 1993.
	8	"Standard Test Access Port and Boundary-Scan Architecture," IEEE Standard Pl149.1-1990, IEEE Standards Board, May 1990.
	9	A. J. van de Goor, Testing semiconductor memories: theory and practice, John Wiley & Sons, Inc., New York, NY, 1991
	10	Magdy S. Abadir , Hassan K. Reghbati, Functional Testing of Semiconductor Random Access Memories, ACM Computing Surveys (CSUR), v.15 n.3, p.175-198, Sept. 1983 [doi>10.1145/356914.356916]
	11	P. Chen, Built-In Self-Test Configurations for Field Programmable Gate Array Logic Blocks, M.S.E.E.Thesis, University of Kentucky, August, 1995.
	12	C. Spivak, private communications, October, 1995.

CITED BY 9

	Abderrahim Doumar , Hideo Ito, Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.386-405, June 2003
	M. Renovell , J. M. Portal , J. Figueras , Y. Zorian, Testing the Local Interconnect Resources of SRAM-Based FPGA's, Journal of Electronic Testing: Theory and Applications, v.16 n.5, p.513-520, Oct 2000
	M. Renovell , J. M. Portal , J. Figueras , Y. Zorian, RAM-based FPGA's: a test approach for the configurable logic, Proceedings of the conference on Design, automation and test in Europe, p.82-88, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Wei Kang , Fred J. Meyer , Fabrizio Lombardi, An Approach for Detecting Multiple Faulty FPGA Logic Blocks, IEEE Transactions on Computers, v.49 n.1, p.48-54, January 2000
	Michel Renovell , Jean Michel Portal , Joan Figueras , Yervant Zorian, Testing the Interconnect of RAM-Based FPGAs, IEEE Design & Test, v.15 n.1, p.45-50, January 1998
	M. Renovell , J. M. Portal , J. Figueras , Y. Zorian, SRAM-Based FPGAs: Testing the Embedded RAM Modules, Journal of Electronic Testing: Theory and Applications, v.14 n.1-2, p.159-167, Feb./April 1999
	M. Renovell , J. M. Portal , J. Figueras , Y. Zorian, Testing the configurable interconnect/logic interface of SRAM-based FPGA's, Proceedings of the conference on Design, automation and test in Europe, p.122-es, January 1999, Munich, Germany
	M. Renovell , J. M. Portal , J. Figueras , Y. Zorian, An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family, Journal of Electronic Testing: Theory and Applications, v.16 n.3, p.289-299, June 2000
	M. Renovell , J. M. Portal , P. Faure , J. Figueras , Y. Zorian, A Discussion on Test Pattern Generation for FPGA—Implemented Circuits, Journal of Electronic Testing: Theory and Applications, v.17 n.3-4, p.283-290, June-August 2001