Universal switch-module design for symmetric-array-based FPGAs

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Universal switch-module design for symmetric-array-based FPGAs

Full text

Pdf (715 KB)

Source

International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays table of contents

Monterey, California, United States

Pages: 80 - 86

Year of Publication: 1996

ISBN:0-89791-773-1

Authors

Yao-Wen Chang	Department of Computer Sciences, University of Texas at Austin, Austin, Texas
D. F. Wong	Department of Computer Science, Chinese University of Hong Kong, Hong Kong and IBM Corporation, T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY
C. K. Wong

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 30, Citation Count: 7

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/228370.228382 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Michael J. Alexander , Gabriel Robins, New performance-driven FPGA routing algorithms, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.562-567, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217589]
	2	Narasimha B. Bhat , Dwight D. Hill, Routable Technologie Mapping for LUT FPGAs, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.95-98, October 11-14, 1992
	3	Stephen D. Brown , Robert J. Francis , Jonathan Rose , Zvonko G. Vranesic, Field-programmable gate arrays, Kluwer Academic Publishers, Norwell, MA, 1992
	4	S. Brown, J. Rose, and Z. G. Vranesic, "A detailed router for field-programmable gate arrays," IEEE Trans. CAD, pp. 620-627, 1992.
	5	S. Brown, J. Rose, and Z. G. Vranesic, "A stochastic model to predict the rautability of field-programmable gate arrays," IEEE Trans. CAD, pp. 1827-1838, 1993.
	6	Yao-Wen Chang , D. F. Wong , C. K. Wong, FPGA global routing based on a new congestion metric, Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors, p.372, October 02-04, 1995
	7	Yao-Wen Chang , D. F. Wong , C. K. Wong, Design and analysis of FPGA/FPIC switch modules, Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors, p.394-401, October 02-04, 1995
	8	C. -D. Chen, Y. -S. Lee, C. -H. Wu, and Y. -L. Lin, "TRACER-fpga: a router for RAM-based FPGA's," IEEE Trans. CAD, March, 1995.
	9	K. Fujiyoshi, Y. Kajitani, and H. Niitsu, "Design of optimum totally-perfect connection-blocks of FPGA," Proc. ISCAS, pp. 221-224, 1994.
	10	Ronald L. Graham , Donald E. Knuth , Oren Patashnik, Concrete mathematics: a foundation for computer science, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1989
	11	H.C. Hsieh, et al., "Third-generation architecture boosts speed and density of field-programmable gate arrays," Prec. CICC, pp. 31.2.1-31.2.7, 1990.
	12	G. Lemieux and S. Brown, "A detailed routing algorithm for allocating wire segments in field-programmable gate arrays," Prec. Physical Design Workshop, 1993.
	13	Chih-chang Lin , Malgorzata Marek-Sadowska , Duane Gatlin, Universal logic gate for FPGA design, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.164-168, November 06-10, 1994, San Jose, California, United States
	14	M. Palczewski, Plane parallel a maze router and its application to FPGAs, Proceedings of the 29th ACM/IEEE conference on Design automation, p.691-697, June 08-12, 1992, Anaheim, California, United States
	15	J. Rose and S. Brown, "Flexibility of interconnection structures for field-programmable gate arrays," IEEE JSSC, pp 277-282, 1991.
	16	J. Rose, R. Francis, D. Lewis, and P. Chow, "Architecture of programmable gate arrays: The effect of logic block functionality on area efficiency," IEEE JSSC, pp. 1217-1225, 1990.
	17	Yachyang Sun , Ting-Chi Wang , C. K. Wong , C. L. Liu, Routing for symmetric FPGAs and FPICs, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.486-490, November 07-11, 1993, Santa Clara, California, United States
	18	Shashidhar Thakur , D. F. Wong, On designing ULM-based FPGA logic modules, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.3-9, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201311]
	19	Stephen M. Trimberger, Field-Programmable Gate Array Technology, Kluwer Academic Publishers, Norwell, MA, 1994
	20	Steven Trimberger , Mon-Ren Chene, Placement-Based Partitioning for Lookup-Table-Based FPGAs, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.91-94, October 11-14, 1992
	21	Yu-Liang Wu , Douglas Chang, On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.362-366, November 06-10, 1994, San Jose, California, United States
	22	Y.-L. Wu, S. Tsukiyama, and M. Marek-Sadowska, "Computational complexity of 2-D FPGA routing for arbitrary switch box topologies," Prec. FPGA'gJ, 1994.
	23	Xilinx Inc., The Programmable Logic Data Book, 1994.
	24	Kai Zhu , D. F. Wong , Yao-Wen Chang, Switch module design with application to two-dimensional segmentation design, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.480-485, November 07-11, 1993, Santa Clara, California, United States

CITED BY 7

	Yao-Wen Chang , Kai Zhu , Guang-Ming Wu , D. F. Wong , C. K. Wong, Analysis of FPGA/FPIC switch modules, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.1, p.11-37, January 2003
	Bin Liu , Fabrizio Lombardi , Nohpill Park , Minsu Choi, Testing Layered Interconnection Networks, IEEE Transactions on Computers, v.53 n.6, p.710-722, June 2004
	André DeHon , Raphael Rubin, Design of FPGA interconnect for multilevel metallization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.10, p.1038-1050, October 2004
	Raphael Rubin , André DeHon, Design of FPGA interconnect for multilevel metalization, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Jing Huang , Mehdi Baradaran Tahoori , Fabrizio Lombardi, Fault tolerance of switch blocks and switch block arrays in FPGA, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.7, p.794-807, July 2005
	J. Huang , M. B. Tahoori , F. Lombardi, Fault Tolerance of Programmable Switch Blocks, Proceedings of the conference on Design, automation and test in Europe, p.21358, February 16-20, 2004
	Ian Kuon , Russell Tessier , Jonathan Rose, FPGA Architecture: Survey and Challenges, Foundations and Trends® in Electronic Design Automation, v.2 n.2, p.135-253, February 2008