Entropy, counting, and programmable interconnect

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Entropy, counting, and programmable interconnect

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays table of contents

Monterey, California, United States

Pages: 73 - 79

Year of Publication: 1996

ISBN:0-89791-773-1

Author

André DeHon

MIT Artificial Intelligence Laboratory, NE43-791, 545 Technology Sq., Cambridge, MA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 18, Citation Count: 8

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Altera Corporation, 2610 Orchard Parkway, San Jose, CA 95134-2020. FLEX 8000 Handbook, May 1994.
	2	Altera Corporation, 2610 Orchard Parkway, San Jose, CA 95134-2020. Data Book, March 1995.
	3	Stephen D. Brown , Robert J. Francis , Jonathan Rose , Zvonko G. Vranesic, Field-programmable gate arrays, Kluwer Academic Publishers, Norwell, MA, 1992
	4	Richard Guo, Hung Nguyen, Adi Srinivasan, Quaid Nasir, Hong Cai, Steve Law, and Amar Mohsen. A Novel Reprogrammable Interconnect Architecture with Decoded RAM Storage. In Proceedings of the IEEE 1994 Custom Integrated Circuits Conference, pages 193-196. IEEE, May 1994.
	5	B. Schoner , C. Jones , J. Villasenor, Issues in wireless video coding using run-time-reconfigurable FPGAs, Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines, p.85, April 19-21, 1995
	6	Jonathan Rose and Stephen Brown. Flexibility oflnterconnection Structures for Field-Programmable Gate Arrays. IEEE Journal of Solid-State Circuits, 26(3):277-282, March 1991.
	7	Edward Tau, Ian Eslick, Derrick Chen, Jeremy Brown, and Andr6 DeHon. A First Generation DPGA Implementation. In Proceedings of the Third Canadian Workshop on Field- Programmable Devices, pages 138-143, May 1995.
	8	M. J. Wirthlin, A dynamic instruction set computer, Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines, p.99, April 19-21, 1995
	9	Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. The Programmable Logic Data Book, 1994.
	10	Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. XC5200 Logic Cell array Family Technical Data, preliminary (vl.0) edition, April 1995.

CITED BY 8

	André DeHon, Rent's rule based switching requirements, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.197-204, March 31-April 01, 2001, Sonoma, California, United States
	André DeHon, Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization), Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.69-78, February 21-23, 1999, Monterey, California, United States
	Guy Lemieux , Paul Leventis , David Lewis, Generating highly-routable sparse crossbars for PLDs, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.155-164, February 10-11, 2000, Monterey, California, United States
	Wenyi Feng , Jonathan W. Greene, Post-placement interconnect entropy: how many configuration bits does a programmable logic device need?, Proceedings of the international workshop on System-level interconnect prediction, March 04-05, 2006, Munich, Germany
	Sebastian Lange , Martin Middendorf, Design Aspects of Multi-level Reconfigurable Architectures, Journal of Signal Processing Systems, v.51 n.1, p.23-37, April 2008
	Wenyi Feng , Sinan Kaptanoglu, Designing efficient input interconnect blocks for LUT clusters using counting and entropy, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, February 18-20, 2007, Monterey, California, USA
	Wenyi Feng , Sinan Kaptanoglu, Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy, ACM Transactions on Reconfigurable Technology and Systems (TRETS), v.1 n.1, p.1-28, March 2008
	Wenyi Feng , Jonathan W. Greene, Post-placement interconnect entropy, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.8, p.945-948, August 2007