| A method for generating random circuits and its application to routability measurement |
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International Symposium on Field Programmable Gate Arrays
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Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
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Monterey, California, United States
Pages: 66 - 72
Year of Publication: 1996
ISBN:0-89791-773-1
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Downloads (6 Weeks): 0, Downloads (12 Months): 19, Citation Count: 19
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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien, On routability prediction for field-programmable gate arrays, Proceedings of the 30th international conference on Design automation, p.326-330, June 14-18, 1993, Dallas, Texas, United States
[doi> 10.1145/157485.164915]
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Wilm E. Donath. Placement and average interconnection lengths of computer logic. IEEE Transactions on Circuits and Systems, CA$-26(4), April 1979.
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Michael Feuer. Connectivity of random logic. IEEE Transactions on Computers, C- 31(1):29-33, January 1982.
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A. E1 Gamal. Two-dimensional stochastic model for interconnections of master slice integrated circuits. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, CAS-28(2):127- 138, February 1981.
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J.L. Kouloheris and A. E1 Gamal. Fpga area versus cell granularity- lookup tables and pla cells. In FPGA '92, pages 9-14, 1992.
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Johnathan Rose, Robert J. Francis, David Lewis, and Paul Chow. Architecture of fieldprogrammable gate arrays: the effect of logic block functionality on area efficiency. IEEE Journal of Solid State Circuits, 25(5):1217- 1225, October 1990.
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SCK93
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Martine Schlag, Pak Chan, and Jackson Kong. Empirical evaluation of multilevel logic minimization tools for a lookup-tablebased field-programmable gate array technology. IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, 12(5):713-22, may 1993.
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Martine Schalg, Jackson Kong, and Pak Chan. Routability-driven technology mapping for lookup table-based fpgas. IEEE Transactions on CAD, 13(1):13-26, January 1994.
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Y.C. Wet and C.K. Cheng. Ratio cut partitioning for hierarchical designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 10(7), July 1991.
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CITED BY 19
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Joachim Pistorius , Edmée Legai , Michel Minoux, Generation of very large circuits to benchmark the partitioning of FPGA, Proceedings of the 1999 international symposium on Physical design, p.67-73, April 12-14, 1999, Monterey, California, United States
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Nevin Kapur , Debabrata Ghosh , Franc Brglez, Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions, Proceedings of the 1997 international symposium on Physical design, p.136-143, April 14-16, 1997, Napa Valley, California, United States
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D. Ghosh , N. Kapur , J. Harlow, III , F. Brglez, Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking, Proceedings of the conference on Design, automation and test in Europe, p.656-663, February 23-26, 1998, Le Palais des Congrés de Paris, France
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Dirk Stroobandt , Peter Verplaetse , Jan van Campenhout, Towards synthetic benchmark circuits for evaluating timing-driven CAD tools, Proceedings of the 1999 international symposium on Physical design, p.60-66, April 12-14, 1999, Monterey, California, United States
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Michael Hutton , J. P. Grossman , Jonathan Rose , Derek Corneil, Characterization and parameterized random generation of digital circuits, Proceedings of the 33rd annual conference on Design automation, p.94-99, June 03-07, 1996, Las Vegas, Nevada, United States
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Arifur Rahman , Shamik Das , Anantha Chandraksan , Rafael Reif, Wiring requirement and three-dimensional integration of field-programmable gate arrays, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.107-113, March 31-April 01, 2001, Sonoma, California, United States
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Christopher Inacio , Herman Schmit , David Nagle , Andrew Ryan , Donald E. Thomas , Yingfai Tong , Ben Klass, Vertical benchmarks for CAD, Proceedings of the 36th ACM/IEEE conference on Design automation, p.408-413, June 21-25, 1999, New Orleans, Louisiana, United States
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Michael Hutton , Jonathan Rose , Derek Corneil, Generation of synthetic sequential benchmark circuits, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.149-155, February 09-11, 1997, Monterey, California, United States
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Young-Su Kwon , Payam Lajevardi , Anantha P. Chandrakasan , Frank Honoré , Donald E. Troxel, A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool, Proceedings of the 2005 international workshop on System level interconnect prediction, April 02-03, 2005, San Francisco, California, USA
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