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Area-speed tradeoffs for hierarchical field-programmable gate arrays
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Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays table of contents
Monterey, California, United States
Pages: 51 - 57  
Year of Publication: 1996
ISBN:0-89791-773-1
Authors
Vi Cuong Chan  University of Toronto, Department of Electrical and Computer Engineering
David M. Lewis  University of Toronto, Department of Electrical and Computer Engineering
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 10,   Citation Count: 1
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Aditya A. Aggarwal, "Routing Architectures for Hierarchical FPGAs", M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of Toronto, 1994.
 
2
ISCAS '85 Test Generation Benchmark Data obtained from the Microelectronics Centre of North Carolina (MCNC)
 
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S. Singh, J. Rose, D. Lewis, K. Chung and P. Chow, "Optimization of Field-Programmable Gate Array Logic Block Architecture for Speed", Proceedings of the 1991 Custom Integrated Circuits Conference (CICC-91), May 1991, pp. 6.1.1-6.1.6.
 
5
J. Rose, R. J. Francis, D. Lewis, P. Chow, "Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency", IEEE Journal of Solid State Circuits (JSSC), Vol. 25, No. 5, Oct. 1990, pp. 1217-1225.
 
6
S. Singh, "The Effect of Logic Block Architecture on FPGA Performance", M.A.Sc. Thesis, Department of Electrical Engineering, University of Toronto, 1991.
 
7
K. Chung, S. Singh, J. Rose and P. Chow, "Using Hierarchical Logic Blocks to Improve the Speed of Field-Programmable Gate Arrays", Proceedings of the First International Workshop on Field Programmable Logic and Applications, Oxford, Sept. 1991, pp. 103-113.
 
8
J. Rose and S. Brown, "Flexibility of Interconnection Structures in Field Programmable Gate Arrays", IEEE Journal of Solid State Circuits (JSSC), Vol. 26, No. 3, March 1991, pp. 277-282.
 
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10
The Programmable Logic Data Book, Xilinx Inc., 1994.
 
11
Vi C. Chan, "Timing Optimization for Hierarchical FPGAs", M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of Toronto, 1995.
 
12
R. Brayton, R. Rudell, A. Sangiovanni Vincentelli and A. Wang, "MIS: a Multiple-Level Logic Optimization System", IEEE Transactions on CAD (TCAD), Vol CAD-6, No. 6, Nov. 1987, pp. 1062-1081.
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14
J. Rose, Z. Vranesic and W. M. Snelgrove, "ALTOR: An automatic standard cell layout program", in Proceeding of the Canadian Conference on VLSI, Nov. 1985, pp. 168-173.
 
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16
B. W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs", Bell System Tech. Journal, 49, 2, 1970, pp. 291-308.
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18
P. S. Hauge, R. Nair and E. J. Yoffa, "Circuit Placement for Predictable Performance", IEEE Proc. of ICCAD, 1987, pp. 88-91.
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21
Altera Corp., "Flex 8000 Handbook", 1994


Collaborative Colleagues:
Vi Cuong Chan: colleagues
David M. Lewis: colleague listing is not available.