|
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Aditya A. Aggarwal, "Routing Architectures for Hierarchical FPGAs", M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of Toronto, 1994.
|
| |
2
|
ISCAS '85 Test Generation Benchmark Data obtained from the Microelectronics Centre of North Carolina (MCNC)
|
| |
3
|
|
| |
4
|
S. Singh, J. Rose, D. Lewis, K. Chung and P. Chow, "Optimization of Field-Programmable Gate Array Logic Block Architecture for Speed", Proceedings of the 1991 Custom Integrated Circuits Conference (CICC-91), May 1991, pp. 6.1.1-6.1.6.
|
| |
5
|
J. Rose, R. J. Francis, D. Lewis, P. Chow, "Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency", IEEE Journal of Solid State Circuits (JSSC), Vol. 25, No. 5, Oct. 1990, pp. 1217-1225.
|
| |
6
|
S. Singh, "The Effect of Logic Block Architecture on FPGA Performance", M.A.Sc. Thesis, Department of Electrical Engineering, University of Toronto, 1991.
|
| |
7
|
K. Chung, S. Singh, J. Rose and P. Chow, "Using Hierarchical Logic Blocks to Improve the Speed of Field-Programmable Gate Arrays", Proceedings of the First International Workshop on Field Programmable Logic and Applications, Oxford, Sept. 1991, pp. 103-113.
|
| |
8
|
J. Rose and S. Brown, "Flexibility of Interconnection Structures in Field Programmable Gate Arrays", IEEE Journal of Solid State Circuits (JSSC), Vol. 26, No. 3, March 1991, pp. 277-282.
|
| |
9
|
|
| |
10
|
The Programmable Logic Data Book, Xilinx Inc., 1994.
|
| |
11
|
Vi C. Chan, "Timing Optimization for Hierarchical FPGAs", M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of Toronto, 1995.
|
| |
12
|
R. Brayton, R. Rudell, A. Sangiovanni Vincentelli and A. Wang, "MIS: a Multiple-Level Logic Optimization System", IEEE Transactions on CAD (TCAD), Vol CAD-6, No. 6, Nov. 1987, pp. 1062-1081.
|
 |
13
|
Robert Francis , Jonathan Rose , Zvonko Vranesic, Chortle-crf: Fast technology mapping for lookup table-based FPGAs, Proceedings of the 28th conference on ACM/IEEE design automation, p.227-233, June 17-22, 1991, San Francisco, California, United States
[doi> 10.1145/127601.127670]
|
| |
14
|
J. Rose, Z. Vranesic and W. M. Snelgrove, "ALTOR: An automatic standard cell layout program", in Proceeding of the Canadian Conference on VLSI, Nov. 1985, pp. 168-173.
|
| |
15
|
|
| |
16
|
B. W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs", Bell System Tech. Journal, 49, 2, 1970, pp. 291-308.
|
 |
17
|
Wilm E. Donath , Reini J. Norman , Bhuwan K. Agrawal , Stephen E. Bello , Sang Yong Han , Jerome M. Kurtzberg , Paul Lowy , Roger I. McMillan, Timing driven placement using complete path delays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.84-89, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123232]
|
| |
18
|
P. S. Hauge, R. Nair and E. J. Yoffa, "Circuit Placement for Predictable Performance", IEEE Proc. of ICCAD, 1987, pp. 88-91.
|
 |
19
|
|
| |
20
|
|
| |
21
|
Altera Corp., "Flex 8000 Handbook", 1994
|
|