Hybrid FPGA architecture

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Hybrid FPGA architecture

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays table of contents

Monterey, California, United States

Pages: 3 - 9

Year of Publication: 1996

ISBN:0-89791-773-1

Authors

Alireza Kaviani	Department of Electrical and Computer Engineering, University of Toronto, Canada
Stephen Brown	Department of Electrical and Computer Engineering, University of Toronto, Canada

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 26, Citation Count: 5

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	CD94	Jason Cong , Yuzheng Ding, An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.48-53, November 1992, Santa Clara, California, United States
	FS94	A.H. Farrahi and M. Sarrafzadeh, "Complexity of the Lookup-Table Minimization Problem for FPGA Technology Mapping," IEEE trans, on computer-aided design of integrated circuits and systems, Nov. 1994.
	HR93	J. He and J. Rose, "Advantages of Heterogeneous Logic Block Architectures for FPGAs," Proceedings of 1993 Custom Integrated Circuits Conference, San Diego, May 1993 pp. 7.4.1 - 7.4.5
	KE91	J.L. Kouloheris and A. E1 Gamal, "FPGA Performance vs. Cell Granularity," Proceedings of the 1991 Custom Integrated Circuits Conference.
	KE92	J. L. Kouloheris and A. E1 Gamal, "PLA-based FPGA Area vs. Cell Granularity," Proceedings of the 1992 Custom Integrated Circuits Conference.
	RFLC90	J. Rose, R.J. Francis, D. Lewis, and P. Chow, "Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency," IEEE JSSC, Vol. 25 No. 5, October 1990, pp. 1217-1225.
	S92	E.M. Sentovich et al., "SIS: A System for Sequential Circuit Synthesis," Electronics Research Laboratory, Memorandum No. UCB/ERL M92/41.
	SP95	Tony Stansfield , Ian Page, The Design of a New FPGA Architecture, Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications, p.1-14, September 01, 1995
	WRV95	Steven J. E. Wilton , Jonathan Rose , Zvonko G. Vranesic, Architecture of centralized field-configurable memory, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.97-103, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201326]

CITED BY 5

	Frank Heile , Andrew Leaver, Hybrid product term and LUT based architectures using embedded memory blocks, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.13-16, February 21-23, 1999, Monterey, California, United States
	Somnath Paul , Swarup Bhunia, Reconfigurable computing using content addressable memory for improved performance and resource usage, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Jason Meyer , Fatih Kocan, Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.2, p.182-195, February 2007
	Yu Hu , Satyaki Das , Steve Trimberger , Lei He, Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Ian Kuon , Russell Tessier , Jonathan Rose, FPGA Architecture: Survey and Challenges, Foundations and Trends® in Electronic Design Automation, v.2 n.2, p.135-253, February 2008