Decoupling integer execution in superscalar processors

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Decoupling integer execution in superscalar processors

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International Symposium on Microarchitecture archive
Proceedings of the 28th annual international symposium on Microarchitecture table of contents

Ann Arbor, Michigan, United States

Pages: 285 - 290

Year of Publication: 1995

ISBN:0-8186-7349-4

Authors

Subbarao Palacharla	Computer Sciences Department, University of Wisconsin-Madison, Madison, WI
J. E. Smith	Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, WI

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE-CS\TCMM : TC on Microprocessors & Microcomputers

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 16, Citation Count: 6

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Linley Gwennap. MIPS R10000 Uses Decoupled Architecture. Microprocessor Report, 8(14), October 1994.
	2	Linley Gwennap. Ultrasparc Unleashes SPARC Performance. Microprocessor Report, 8(13), October 1994.
	3	A.R. Pleszkun and E.S. Davidson. Structured Memory Access Architecture. In International Conference on Parallel Processing, pages 461-471, 1983.
	4	Richard M. Russell, The CRAY-1 computer system, Communications of the ACM, v.21 n.1, p.63-72, Jan. 1978 [doi>10.1145/359327.359336]
	5	Michael Slater. AMD's K5 Designed to Outrun Pentium. Microprocessor Report, 8(14), October 1994.
	6	James E. Smith, Decoupled access/execute computer architectures, Proceedings of the 9th annual symposium on Computer Architecture, p.112-119, April 26-29, 1982, Austin, Texas, United States
	7	J. E. Smith , G. E. Dermer , B. D. Vanderwarn , S. D. Klinger , C. M. Rozewski, The ZS-1 central processor, Proceedings of the second international conference on Architectual support for programming languages and operating systems, p.199-204, October 1987, Palo Alto, California, United States
	8	SPEC. (entire issue). SPEC Newsletter, 3(4), December 1991.
	9	Sun Microsystems Laboratories, Inc. Introduction to Shade, April 1993.
	10	Mark Weiser. Program Slicing. IEEE Transactions on Software Engineering, 10(4):352-357, July 1984.

CITED BY 6

	Ramon Canal , Joan-Manuel Parcerisa , Antonio González, Dynamic Code Partitioning for Clustered Architectures, International Journal of Parallel Programming, v.29 n.1, p.59-79, February 2001
	Joan-Manuel Parcerisa , Antonio Gonzalez, Improving Latency Tolerance of Multithreading through Decoupling, IEEE Transactions on Computers, v.50 n.10, p.1084-1094, October 2001
	S. Subramanya Sastry , Subbarao Palacharla , James E. Smith, Exploiting idle floating-point resources for integer execution, ACM SIGPLAN Notices, v.33 n.5, p.118-129, May 1998
	Pierre Salverda , Craig Zilles, A Criticality Analysis of Clustering in Superscalar Processors, Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, p.55-66, November 12-16, 2005, Barcelona, Spain
	Alastair D. Reid , Krisztian Flautner , Edmund Grimley-Evans , Yuan Lin, SoC-C: efficient programming abstractions for heterogeneous multicore systems on chip, Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, October 19-24, 2008, Atlanta, GA, USA
	Fang Lu , Lei Wang , Xiaobing Feng , Zhiyuan Li , Zhaoqing Zhang, Exploiting idle register classes for fast spill destination, Proceedings of the 22nd annual international conference on Supercomputing, June 07-12, 2008, Island of Kos, Greece