Efficient instruction scheduling using finite state automata

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Efficient instruction scheduling using finite state automata

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International Symposium on Microarchitecture archive
Proceedings of the 28th annual international symposium on Microarchitecture table of contents

Ann Arbor, Michigan, United States

Pages: 46 - 56

Year of Publication: 1995

ISBN:0-8186-7349-4

Authors

Vasanth Bala	Hewlett Packard Labs
Norman Rubin	Digital Equipment Corp.

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE-CS\TCMM : TC on Microprocessors & Microcomputers

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 35, Citation Count: 12

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	7	Raymond Lo , Sun Chan , Fred Chow , Shin-Ming Liu, Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distribution, Proceedings of the 27th annual international symposium on Microarchitecture, p.148-152, November 30-December 02, 1994, San Jose, California, United States [doi>10.1145/192724.192745]
	8	P. Geoffrey Lowney , Stefan M. Freudenberger , Thomas J. Karzes , W. D. Lichtenstein , Robert P. Nix , John S. O'Donnell , John Ruttenberg, The multiflow trace scheduling compiler, The Journal of Supercomputing, v.7 n.1-2, p.51-142, May 1993 [doi>10.1007/BF01205182]
	9	Thomas Müller, Employing finite automata for resource scheduling, Proceedings of the 26th annual international symposium on Microarchitecture, p.12-20, December 01-03, 1993, Austin, Texas, United States
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	11	B. Ramakrishna Rau , Michael S. Schlansker , P. P. Tirumalai, Code generation schema for modulo scheduled loops, Proceedings of the 25th annual international symposium on Microarchitecture, p.158-169, December 01-04, 1992, Portland, Oregon, United States
	12	Pei-Chi Wu , Feng-Jian Wang , Kai-Ru Young, Scanning regular languages by dual finite automata, ACM SIGPLAN Notices, v.27 n.4, p.12-16, April 1992 [doi>10.1145/131080.131081]

CITED BY 12

	R. Govindarajan , N. S. S. Narasimha Rao , E. R. Altman , Guang R. Gao, Enhanced Co-Scheduling: A Software Pipelining Method Using Modulo-Scheduled Pipeline Theory, International Journal of Parallel Programming, v.28 n.1, p.1-46, February 2000
	Alexandre E. Eichenberger , Edward S. Davidson, A reduced multipipeline machine description that preserves scheduling constraints, ACM SIGPLAN Notices, v.31 n.5, p.12-22, May 1996
	V. Janaki Ramanan , R. Govindarajan, Resource usage models for instruction scheduling: two new models and a classification, Proceedings of the 13th international conference on Supercomputing, p.417-424, June 20-25, 1999, Rhodes, Greece
	Gang Chen , Michael D. Smith, Reorganizing global schedules for register allocation, Proceedings of the 13th international conference on Supercomputing, p.408-416, June 20-25, 1999, Rhodes, Greece
	John C. Gyllenhaal , Wen-mei W. Hwu , B. Ramabriohna Rau, Optimization of machine descriptions for efficient use, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.349-358, December 02-04, 1996, Paris, France
	Qin Zhao , Bart Mesman , Twan Basten, Static resource models for code-size efficient embedded processors, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.2, p.219-250, May 2003
	Josep M. Codina , Josep Llosa , Antonio González, A comparative study of modulo scheduling techniques, Proceedings of the 16th international conference on Supercomputing, June 22-26, 2002, New York, New York, USA
	Oliver Wahlen , Manuel Hohenauer , Rainer Leupers , Heinrich Meyr, Instruction Scheduler Generation for Retargetable Compilation, IEEE Design & Test, v.20 n.1, p.34-41, January 2003
	Thomas M. Conte , Sumedh Sathaye, Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility, IEEE Transactions on Computers, v.49 n.8, p.814-825, August 2000
	K. Ananda Vardhan , Y. N. Srikant, Transition aware scheduling: increasing continuous idle-periods in resource units, Proceedings of the 2nd conference on Computing frontiers, May 04-06, 2005, Ischia, Italy
	Matthew J. Bridges , Neil Vachharajani , Guilherme Ottoni , David I. August, Automatic instruction scheduler retargeting by reverse-engineering, ACM SIGPLAN Notices, v.41 n.6, June 2006
	Steve Haga , Andrew Webber , Yi Zhang , Nghi Nguyen , Rajeev Barua, Reducing code size in VLIW instruction scheduling, Journal of Embedded Computing, v.1 n.3, p.415-433, August 2005