| The performance impact of incomplete bypassing in processor pipelines |
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International Symposium on Microarchitecture
archive
Proceedings of the 28th annual international symposium on Microarchitecture
table of contents
Ann Arbor, Michigan, United States
Pages: 36 - 45
Year of Publication: 1995
ISBN:0-8186-7349-4
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Authors
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Pritpal S. Ahuja
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Department of Computer Science, Princeton University, 35 Olden Street, Princeton, New Jersey
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Douglas W. Clark
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Department of Computer Science, Princeton University, 35 Olden Street, Princeton, New Jersey
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Anne Rogers
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Department of Computer Science, Princeton University, 35 Olden Street, Princeton, New Jersey
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IEEE Computer Society Press
Los Alamitos, CA, USA
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| Bibliometrics |
Downloads (6 Weeks): 3, Downloads (12 Months): 16, Citation Count: 11
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Andrea Capitanio , Nikil Dutt , Alexandru Nicolau, Partitioned register files for VLIWs: a preliminary analysis of tradeoffs, Proceedings of the 25th annual international symposium on Microarchitecture, p.292-300, December 01-04, 1992, Portland, Oregon, United States
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Robert Cohn , Thomas Gross , Monica Lam, Architecture and compiler tradeoffs for a long instruction wordprocessor, Proceedings of the third international conference on Architectural support for programming languages and operating systems, p.2-14, April 03-06, 1989, Boston, Massachusetts, United States
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D. Dobberpuhl et al. A 200-MHz 64-b Dual-Issue CMOS Microprocessor. IEEE J. of Solid-State Circuits, 27(11):1555-1564, November 1992.
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J. A. Fisher. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Transactions on Computers, C-30(7):478-490, 1981.
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J. Gray, A. Naylor, A. Abnous, and N. Bagherzadeh. VIPER: A VLIW Integer Microprocessor. IEEE Journal of Sohd State Circuits, 28(12):1377-1383, December 1993.
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J. R. Larus. Assemblers, Linkers, and the SPIM Simulator. Appendix A of Computer Organization ~ Design: the Hardware/Software Interface, D. A. Patterson and J. L. Hennessy, Morgan Kaufmann, 1994.
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P. Geoffrey Lowney , Stefan M. Freudenberger , Thomas J. Karzes , W. D. Lichtenstein , Robert P. Nix , John S. O'Donnell , John Ruttenberg, The multiflow trace scheduling compiler, The Journal of Supercomputing, v.7 n.1-2, p.51-142, May 1993
[doi> 10.1007/BF01205182]
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CITED BY 11
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Marcio Buss , Rodolfo Azevedo , Paulo Centoducatte , Guido Araujo, Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures, Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, November 16-17, 2001, Atlanta, Georgia, USA
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Manjunath Kudlur , Kevin Fan , Michael Chu , Rajiv Ravindran , Nathan Clark , Scott Mahlke, FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths, Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, p.201, March 20-24, 2004, Palo Alto, California
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Sanghyun Park , Eugene Earlie , Aviral Shrivastava , Alex Nicolau , Nikil Dutt , Yunheung Paek, Automatic generation of operation tables for fast exploration of bypasses in embedded processors, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
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