A multiple-dominance switch-level model for simulation of short faults

ABSTRACT

Short faults in CMOS networks frequently give rise to intermediate node voltages. An efficient local algorithm is presented for event-driven switch-level simulation of CMOS networks in which intermediate signal values are common. The proposed model allows multiple dominant signals associated with the state of a node. The strength of several logical low and high signal contributions can thereby be taken into account when the logic state of a node is computed, which means that intermediate voltages can be handled more accurately. To demonstrate the usefulness of the multiple-dominance model in fault simulations, a new fault simulation algorithm is presented. Various common transistor-level fault types were simulated, and the results show that the number of discrepancies from electrical-level simulations is significantly reduced at a low computational cost.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

General Terms:
Algorithms, Measurement, Performance, Theory

Keywords:
Logic simulation, Fault simulation, intermediate logic values