A high-level design and optimization tool for analog RF receiver front-ends

ABSTRACT

This paper presents a high-level analysis and optimization tool for the design of analog RF receiver front-ends, which takes all design parameters and all aspects of performance degradation (noise, distortion, self-mixing...) into account. The simulations are performed in the spectral domain with a behavioral model library for the RF building blocks. The tool allows to explore alternative RF receiver topologies as well as to investigate design trade-offs within each topology. By having integrated the performance analysis routine within a simulated annealing optimization loop, the tool can also perform an optimal high-level synthesis of a given topology towards a specific application. It then determines the optimal specifications for the RF building blocks such that the required receiver signal quality is met while the overall power and/or area consumption is minimized.

REFERENCES

• 1: J. Sevenhans et al., "An analog radio front-end chip set for a 1.9 GHz mobile radio telephone application," proc. ISSCC, pp.44-45, Feb. 1994.
• 2: C. Marshall et al., "A 2.7V GSM transceiver ICs with onchip filtering," proc. ISSCC, pp. 148-149, Feb. 1995.
• 3: T. Stetzler et al., "A 2.7V to 4.5V single-chip GSM transceiver RF integrated circuit," proc. ISSCC, pp. 150-151, Feb. 1995.
• 4: K. Kundert, A. Sangiovanni-Vincentelli, "Simulation of nonlinear circuits in the frequency domain," IEEE Trans. on Computer-Aided Design, Vol. 5, No. 4, pp. 521-535, Oct. 1986.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Signal processing systems

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

  J. Computer Applications

General Terms:
Design, Measurement, Performance, Theory

Keywords:
analog CAD, analog high-level synthesis, RF design and optimization