Rectangle-packing-based module placement

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Rectangle-packing-based module placement

Full text

Publisher Site , Pdf

Pdf (261 KB)

Source

International Conference on Computer Aided Design archive
Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 472 - 479

Year of Publication: 1995

ISBN:0-8186-7213-7

Authors

Hiroshi Murata	School of Information Science, Japan Advanced Institute of Science and Technology, Tatsunokuchi, Ishikawa 923-12, Japan
Kunihiro Fujiyoshi	School of Information Science, Japan Advanced Institute of Science and Technology, Tatsunokuchi, Ishikawa 923-12, Japan
Shigetoshi Nakatake	School of Information Science, Japan Advanced Institute of Science and Technology, Tatsunokuchi, Ishikawa 923-12, Japan
Yoji Kajitani	Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Meguro-ku, Tokyo 152, Japan

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 15, Downloads (12 Months): 92, Citation Count: 101

Additional Information:

abstract references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

ABSTRACT

The first and the most critical stage in VLSI layout design is the placement, the background of which is the rectangle packing problem: Given many rectangular modules of arbitrary size, place them without overlapping on a layer in the smallest bounding rectangle. Since the variety of the packing is infinite (two- dimensionally continuous) many, the key issue for successful optimization is in the introduction of a P-admissible solution space, which is a finite set of solutions at least one of which is optimal. This paper proposes such a solution space where each packing is represented by a pair of module name sequences. Searching this space by simulated annealing, hundreds of modules could be successfully packed as demonstrated. Combining a conventional wiring method, the biggest MCNC benchmark ami49 is challenged.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	B.S.Baker, E.G.Coffman, and R.L.Rivest, "Orthogonal Packings in Two Dimensions," SIAM J. Comput., vol. 9, no. 4, pp. 846-855, 1980.
	2	Lu Sha , Robert W. Dutton, An analytical algorithm for placement of arbitrarily sized rectangular blocks, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.602-608, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317952]
	3	A.Alon and U.Ascher, "Model and Solution Strategy for Placement of Rectangular Blocks in the Euclidean Plane," IEEE Trans. on CAD, vol. 7, no. 3, pp. 378- 386, 1988.
	4	Y.G.Saab and V.B.Rao, "Combinatorial Optimization by Stochastic Evolution," IEEE Trans. on CAD, vol. CAD-10, no. 4, pp. 525-535, 1991.
	5	Ralph H.J.M. Otten, Automatic floorplan design, Proceedings of the 19th conference on Design automation, p.261-267, January 1982
	6	D. F. Wong , C. L. Liu, A new algorithm for floorplan design, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.101-107, July 1986, Las Vegas, Nevada, United States
	7	W.M.Dai and E.Kuh, "Simaltaneous Floorplanning and Global Routing for Hierarchical Building Block Layout," IEEE Trans. on CAD, vol. CAD-6, no. 5, pp. 828-837, 1987.
	8	Ting-chi Wang , D. F. Wong, An optimal algorithm for floorplan area optimization, Proceedings of the 27th ACM/IEEE conference on Design automation, p.180-186, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123253]
	9	Hidetoshi Onodera , Yo Taniguchi , Keikichi Tamaru, Branch-and-bound placement for building block layout, Proceedings of the 28th conference on ACM/IEEE design automation, p.433-439, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127708]
	10	Larry Stockmeyer, Optimal orientations of cells in slicing floorplan designs, Information and Control, v.57 n.2-3, p.91-101, May/June 1983 [doi>10.1016/S0019-9958(83)80038-2]
	11	Peichen Pan , Weiping Shi , C. L. Liu, Area minimization for hierarchical floorplans, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.436-440, November 06-10, 1994, San Jose, California, United States

CITED BY 101

	Jai-Ming Lin , Yao-Wen Chang, TCG: a transitive closure graph-based representation for non-slicing floorplans, Proceedings of the 38th conference on Design automation, p.764-769, June 2001, Las Vegas, Nevada, United States
	M. Lai , D. Wong, Slicing tree is a complete floorplan representation, Proceedings of the conference on Design, automation and test in Europe, p.228-232, March 2001, Munich, Germany
	Evangeline F. Y. Young , Chris C. N. Chu , Cien Shen, Twin binary sequences: a non-redundant representation for general non-slicing floorplan, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Andrew B. Kahng, Classical floorplanning harmful?, Proceedings of the 2000 international symposium on Physical design, p.207-213, May 2000, San Diego, California, United States
	Hung-Ming Chen , D. F. Wong , Wai-Kei Mak , Hannah H. Yang, Faster and more accurate wiring evaluation in interconnect-centric floorplanning, Proceedings of the 11th Great Lakes symposium on VLSI, p.62-67, March 2001, West Lafayette, Indiana, United States
	F. Y. Young , D. F. Wong, Slicing floorplans with pre-placed modules, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.252-258, November 08-12, 1998, San Jose, California, United States
	Jason Cong , Tianming Kong , David Zhigang Pan, Buffer block planning for interconnect-driven floorplanning, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.358-363, November 07-11, 1999, San Jose, California, United States
	Jason Cong , Tianming Kong , Faming Liang , Jun S. Liu , Wing Hung Wong , Dongmin Xu, Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application, Proceedings of the 2000 conference on Asia South Pacific design automation, p.277-282, January 2000, Yokohama, Japan
	Faran Rafiq , Malgorzata Chrzanowska-Jeske , Hannah Honghua Yang , Naveed Sherwani, Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Jin Xu , Pei-ning Guo , Chung-Kuan Cheng, Rectilinear block placement using sequence-pair, Proceedings of the 1998 international symposium on Physical design, p.173-178, April 06-08, 1998, Monterey, California, United States
	Probir Sarkar , Vivek Sundararaman , Cheng-Kok Koh, Routability-driven repeater block planning for interconnect-centric floorplanning, Proceedings of the 2000 international symposium on Physical design, p.186-191, May 2000, San Diego, California, United States
	Sheqin Dong , Xianlong Hong , Youliang Wu , Yizhou Lin , Jun Gu, VLSI block placement using less flexibility first principles, Proceedings of the 2001 conference on Asia South Pacific design automation, p.601-604, January 2001, Yokohama, Japan
	Hung-Ming Chen , Hai Zhou , F. Y. YOung , D. F. Wong , Hannah H. Yang , Naveed Sherwani, Integrated floorplanning and interconnect planning, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.354-357, November 07-11, 1999, San Jose, California, United States
	Bo Yao , Hongyu Chen , Chung-Kuan Cheng , Ronald Graham, Revisiting floorplan representations, Proceedings of the 2001 international symposium on Physical design, p.138-143, April 01-04, 2001, Sonoma, California, United States
	Bruno Lévy , Sylvain Petitjean , Nicolas Ray , Jérome Maillot, Least squares conformal maps for automatic texture atlas generation, ACM Transactions on Graphics (TOG), v.21 n.3, July 2002
	Maggie Zhi-Wei Kang , Wayne Wei-Ming Dai, Topology constrained rectilinear block packing for layout reuse, Proceedings of the 1998 international symposium on Physical design, p.179-186, April 06-08, 1998, Monterey, California, United States
	Hiroshi Murata , Ernest S. Kuh, Sequence-pair based placement method for hard/soft/pre-placed modules, Proceedings of the 1998 international symposium on Physical design, p.167-172, April 06-08, 1998, Monterey, California, United States
	Jin Xu , Pei-Ning Guo , Chung-Kuan Cheng, Cluster refinement for block placement, Proceedings of the 34th annual conference on Design automation, p.762-765, June 09-13, 1997, Anaheim, California, United States
	H. Murata , K. Fujiyoshi , M. Kaneko, VLSI/PCB placement with obstacles based on sequence-pair, Proceedings of the 1997 international symposium on Physical design, p.26-31, April 14-16, 1997, Napa Valley, California, United States
	Toshihiko Takahashi, A new encoding scheme for rectangle packing problem, Proceedings of the 2000 conference on Asia South Pacific design automation, p.175-178, January 2000, Yokohama, Japan
	Shigetoshi Nakatake , Kunihiro Fujiyoshi , Hiroshi Murata , Yoji Kajitani, Module placement on BSG-structure and IC layout applications, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.484-491, November 10-14, 1996, San Jose, California, United States
	Yun-Chih Chang , Yao-Wen Chang , Guang-Ming Wu , Shu-Wei Wu, B*-Trees: a new representation for non-slicing floorplans, Proceedings of the 37th conference on Design automation, p.458-463, June 05-09, 2000, Los Angeles, California, United States
	Bo Yao , Hongyu Chen , Chung-Kuan Cheng , Ronald Graham, Floorplan representations: Complexity and connections, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.1, p.55-80, January 2003
	Takayuki Yamanouchi , Kazuo Tamakashi , Takashi Kambe, Hybrid floorplanning based on partial clustering and module restructuring, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.478-483, November 10-14, 1996, San Jose, California, United States
	Kunihiro Fujiyoshi , Hiroshi Murata, Arbitrary convex and concave rectilinear block packing using sequence-pair, Proceedings of the 1999 international symposium on Physical design, p.103-110, April 12-14, 1999, Monterey, California, United States
	Pei-Ning Guo , Chung-Kuan Cheng , Takeshi Yoshimura, An O-tree representation of non-slicing floorplan and its applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.268-273, June 21-25, 1999, New Orleans, Louisiana, United States
	Michael A. Riepe , Karem A. Sakallah, Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis, Proceedings of the 1999 international symposium on Physical design, p.74-81, April 12-14, 1999, Monterey, California, United States
	Maggie Zhiwei Kang , Wayne Wei-Mingi Dai, Arbitrary rectilinear block packing based on sequence pair, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.259-266, November 08-12, 1998, San Jose, California, United States
	Xianlong Hong , Gang Huang , Yici Cai , Jiangchun Gu , Sheqin Dong , Chung Kuan Cheng , Jun Gu, Corner block list: an effective and efficient topological representation of non-slicing floorplan, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Michael A. Riepe , Karem A. Sakallah, Transistor placement for noncomplementary digital VLSI cell synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.1, p.81-107, January 2003
	Hsun-Cheng Lee , Yao-Wen Chang , Jer-Ming Hsu , Hannah H. Yang, Multilevel floorplanning/placement for large-scale modules using B*-trees, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Evangeline F. Y. Young , Chris C. N. Chu , M. L. Ho, Placement constraints in floorplan design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.735-745, July 2004
	Jai-Ming Lin , Yao-Wen Chang , Shih-Ping Lin, Corner sequence: a P-admissible floorplan representation with a worst case linear-time packing scheme, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.679-686, August 2003
	Akira Nagao , Takashi Kambe , Isao Shirakawa, A layout approach to monolithic microwave IC, Proceedings of the 1998 international symposium on Physical design, p.65-72, April 06-08, 1998, Monterey, California, United States
	T. Serdar , C. Sechen, Automatic datapath tile placement and routing, Proceedings of the conference on Design, automation and test in Europe, p.552-559, March 2001, Munich, Germany
	Pedro V. Sander , John Snyder , Steven J. Gortler , Hugues Hoppe, Texture mapping progressive meshes, Proceedings of the 28th annual conference on Computer graphics and interactive techniques, p.409-416, August 2001
	Grzegorz Blakiewicz , Marcin Jeske , Malgorzata Chrzanowska-Jeske , Jin S. Zhang, Substrate noise modeling in early floorplanning of MS-SOCs, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Takashi Nojima , Yasuhiro Takashima , Shigetoshi Nakatake , Yoji Kajitani, A device-level placement with multi-directional convex clustering, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Jingqi Yan , Pengfei Shi , David Zhang, Transforming 3D mesh surfaces into images by parameterization, Integrated image and graphics technologies, Kluwer Academic Publishers, Norwell, MA, 2004
	Chang-Tzu Lin , De-Sheng Chen , Yi-Wen Wang, Robust fixed-outline floorplanning through evolutionary search, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.42-44, January 27-30, 2004, Yokohama, Japan
	Ping-Hung Yuh , Chia-Lin Yang , Yao-Wen Chang , Hsin-Lung Chen, Temporal floorplanning using 3D-subTCG, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.725-730, January 27-30, 2004, Yokohama, Japan
	Jason Cong , Gabriele Nataneli , Michail Romesis , Joseph R. Shinnerl, An area-optimality study of floorplanning, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Jai-Ming Lin , Yao-Wen Chang, TCG-S: orthogonal coupling of P*-admissible representations for general floorplans, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Jason Cong , Tianming Kong , Zhigang (David) Pan, Buffer block planning for interconnect planning and prediction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.929-937, 12/1/2001
	SheQin Dong , XianLong Hong , YuLiang Wu , Jun Gu, Deterministic VLSI block placement algorithm using less flexibility first principle, Journal of Computer Science and Technology, v.18 n.6, p.739-746, November 2003
	Tung-Chieh Chen , Yao-Wen Chang, Modern floorplanning based on fast simulated annealing, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Yong Zhan , Yan Feng , Sachin S. Sapatnekar, A fixed-die floorplanning algorithm using an analytical approach, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Jacob R. Minz , Sung Kyu Lim , Cheng-Kok Koh, 3D module placement for congestion and power noise reduction, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Sung Kyu Lim , Ramprasad Ravichandran , Mike Niemier, Partitioning and placement for buildable QCA circuits, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.1 n.1, p.50-72, April 2005
	Jai-Ming Lin , Guang-Ming Wu , Yao-Wen Chang , Jen-Hui Chuang, Placement with symmetry constraints for analog layout design using TCG-S, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Jason Cong , Michail Romesis , Joseph R. Shinnerl, Fast floorplanning by look-ahead enabled recursive bipartitioning, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Jia Wang , Hai Zhou, Interconnect estimation without packing via ACG floorplans, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Keith W. C. Wong , Evangeline F. Y. Young, Fast buffer planning and congestion optimization in interconnect-driven floorplanning, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Sudarshan Banerjee , Elaheh Bozorgzadeh , Nikil Dutt, Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Shinichi Kouda , Chikaaki Kodama , Kunihiro Fujiyoshi, Improved method of cell placement with symmetry constraints for analog IC layout design, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Sheqin Dong , Xianlong Hong , Xin Qi , Ruijie Wang , Song Chen , Jun Gu, VLSI module placement with pre-placed modules and considering congestion using solution space smoothing, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Jason Cong , Min Xie, A robust detailed placement for mixed-size IC designs, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Iris Hui-Ru Jiang , Yao-Wen Chang , Jing-Yang Jou , Kai-Yuan Chao, Simultaneous floorplanning and buffer block planning, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Guang-Ming Wu , Yun-Chih Chang , Yao-Wen Chang, Rectilinear block placement using B*-trees, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.2, p.188-202, April 2003
	Takashi Nojima , Xiaoke Zhu , Yasuhiro Takashima , Shigetoshi Nakatake , Yoji Kajitani, Multi-level placement with circuit schema based clustering in analog IC layouts, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.406-411, January 27-30, 2004, Yokohama, Japan
	Lei Cheng , Liang Deng , Martin D. F. Wong, Floorplanning for 3-D VLSI design, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Sudarshan Banerjee , Elaheh Bozorgzadeh , Nikil Dutt, PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Aaron N. Ng , Igor L. Markov , Rajat Aggarwal , Venky Ramachandran, Solving hard instances of floorplacement, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Renshen Wang , Sheqin Dong , Xianlong Hong, An improved P-admissible floorplan representation based on Corner Block List, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Keishi Sakanushi , Shigetoshi Nakatake , Yoji Kajitani, The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.267-274, November 08-12, 1998, San Jose, California, United States
	Chikaaki Kodama , Kunihiro Fujiyoshi, Selected sequence-pair: an efficient decodable packing representation in linear time using sequence-pair, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Yu Xia , Malgorzata Chrzanowska-Jeske , Benyi Wang , Marcin Jeske, Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.100, November 09-13, 2003
	Fan Mo , Robert K. Brayton, A simultaneous bus orientation and bused pin flipping algorithm, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	F. Y. Young , D. F. Wong, Slicing floorplans with range constraint, Proceedings of the 1999 international symposium on Physical design, p.97-102, April 12-14, 1999, Monterey, California, United States
	Eric Wong , Sung Kyu Lim, 3D floorplanning with thermal vias, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Michael Healy , Mario Vittes , Mongkol Ekpanyapong , Chinnakrishnan Ballapuram , Sung Kyu Lim , Hsien-Hsin S. Lee , Gabriel H. Loh, Microarchitectural floorplanning under performance and thermal tradeoff, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Fei Su , Krishnendu Chakrabarty, Module placement for fault-tolerant microfluidics-based biochips, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.3, p.682-710, July 2006
	Kristofer Vorwerk , Andrew Kennings , Doris T. Chen , Laleh Behjat, Floorplan repair using dynamic whitespace management, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Eric Wong , Jacob Minz , Sung Kyu Lim, Decoupling capacitor planning and sizing for noise and leakage reduction, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Yiu-Cheong Tam , Evangeline F. Y. Young , Chris Chu, Analog placement with symmetry and other placement constraints, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Chuan Lin , Hai Zhou , Chris Chu, A revisit to floorplan optimization by Lagrangian relaxation, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Lei Cheng , M. D. F. Wong, Floorplan design for multi-million gate FPGAs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.292-299, November 07-11, 2004
	Tung-Chieh Chen , Yao-Wen Chang , Shyh-Chang Lin, IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.159-164, November 06-10, 2005, San Jose, CA
	J. Cong , M. Romesis , J. R. Shinnerl, Robust mixed-size placement under tight white-space constraints, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.165-172, November 06-10, 2005, San Jose, CA
	Sudip Nag , Kamal Chaudhary, Post-placement residual-overlap removal with minimal movement, Proceedings of the conference on Design, automation and test in Europe, p.116-es, January 1999, Munich, Germany
	I-Min Liu , Hung-Ming Chen , Tan-Li Chou , Adnan Aziz , D. F. Wong, Integrated power supply planning and floorplanning, Proceedings of the 2001 conference on Asia South Pacific design automation, p.589-594, January 2001, Yokohama, Japan
	Peter G. Sassone , Sung K. Lim, A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.74, November 09-13, 2003
	Qing Dong , Shigetoshi Nakatake, Constraint-free analog placement with topological symmetry structure, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Evangeline F. Y. Young , M. L. Ho , Chris C. N. Chu, A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.661, January 07-11, 2002
	Nikolaos D. Liveris , Prithviraj Banerjee, Power Aware Interface Synthesis for Bus-Based SoC Designs, Proceedings of the conference on Design, automation and test in Europe, p.20864, February 16-20, 2004
	Ping-Hung Yuh , Chia-Lin Yang , Yao-Wen Chang, Temporal floorplanning using the three-dimensional transitive closure subGraph, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.4, p.37-es, September 2007
	Michael Healy , Fayez Mohamood , Hsien-Hsin S. Lee , Sung Kyu Lim, A unified methodology for power supply noise reduction in modern microarchitecture design, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Ping-Hung Yuh , Chia-Lin Yang , Yao-Wen Chang, Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.3 n.3, p.13-es, November 2007
	Qiang Ma , Evangeline F. Y. Young , K. P. Pun, Analog placement with common centroid constraints, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Chiu-Wing Sham , Evangeline F. Y. Young , Hai Zhou, Optimizing wirelength and routability by searching alternative packings in floorplanning, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-13, January 2008
	Jill H. Y. Law , Evangeline F. Y. Young, Multi-bend bus driven floorplanning, Integration, the VLSI Journal, v.41 n.2, p.306-316, February, 2008
	Dae Hyun Kim , Sung Kyu Lim, Bus-aware microarchitectural floorplanning, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Chao-Hung Lu , Hung-Ming Chen , Chien-Nan Jimmy Liu, Effective decap insertion in area-array SoC floorplan design, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.4, p.1-20, September 2008
	Linfu Xiao , Evangeline F. Y. Young, Analog placement with common centroid and 1-D symmetry constraints, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
	Jarrod A. Roy , Aaron N. Ng , Rajat Aggarwal , Venky Ramachandran , Igor L. Markov, Solving modern mixed-size placement instances, Integration, the VLSI Journal, v.42 n.2, p.262-275, February, 2009
	Sudarshan Banerjee , Elaheh Bozorgzadeh , Nikil D. Dutt, Integrating physical constraints in HW-SW partitioning for architectures with partial dynamic reconfiguration, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.11, p.1189-1202, November 2006
	Ou He , Sheqin Dong , Jinian Bian , Satoshi Goto , Chung-Kuan Cheng, A novel fixed-outline floorplanner with zero deadspace for hierarchical design, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	Qiang Ma , Evangeline F. Y. Young, Network flow-based power optimization under timing constraints in MSV-driven floorplanning, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	Kunihiko Yanagibashi , Yasuhiro Takashima , Yuichi Nakamura, A Relocation Method for Circuit Modifications, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E90-A n.12, p.2743-2751, December 2007
	Toshihiko Takahashi , Ryo Fujimaki, Fujimaki-Takahashi Squeeze: Linear Time Construction of Constraint Graphs of Floorplan for a Given Permutation, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E91-A n.4, p.1071-1076, April 2008
	Roman Gindin , Israel Cidon , Idit Keidar, NoC-Based FPGA: Architecture and Routing, Proceedings of the First International Symposium on Networks-on-Chip, p.253-264, May 07-09, 2007