Gate-level simulation of digital circuits using multi-valued Boolean algebras

ABSTRACT

This paper describes an algorithm for the simulation of gate-level logic. Multiple logic levels are used to describe the state of each node. Each state corresponds to a different voltage level, and the number of levels to be used for a simulation is user-defined. This feature simplifies considerably the interface between a digital and an analog simulator. A DC solver is incorporated to find the initial operating point of a circuit before a transient analysis begins. This solver has the capability of finding the operating point of gates located in feedback loops. For transient analysis, a gate delay model that takes into account the slope of the input waveforms is used. The performance of the algorithm is demonstrated by simulations of a number of benchmark circuits.

REFERENCES

• 1: Genhong Ruan, Jiri Vlach, James A. Barby, and Ajoy Opal, "Analog Functional Simulator for Multilevel Systems", IEEE Transactions on Computer-Aided Design, vol. CAD-10, no. 5, pp. 565-576, May 1991.
• 2: Eduardo L. Acuna, James E Dervenis, Andrew J. Pagones, Fred L. Yang, and Resve A. Saleh, "Simulation Techniques for Mixed Analog/Digital Circuits", IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 353-362, April 1990.
• 3: Young H. Kim, J. E. Kleckner, R. A. Saleh, and A. R. Newton, "Electrical-Logic Simulation", in Proceedings of the 1984 International Conference on Computer-Aided Design. IEEE, November 1984, pp. 7-9.
• 4: Sergiu Rudeanu, Boolean Functions and Equations, North-Holland Publishing Co., Amsterdam, 1974.
• 5: Paul R. Halmos, Lectures on Boolean Algebras, Van Nostrand Co., Princeton, NJ, 1963.
• 6: Melvin A. Breuer, "A Note on Three-Valued Logic Simulation", IEEE Transactions on Computers, vol. C-21, no. 4, pp. 399-402, April 1972.
• 7: Randal E. Bryant, "Algorithmic Aspects of Symbolic Switch Network Analysis", IEEE Transactions on Computer-Aided Design, vol. CAD-6, no. 4, pp. 618- 633, July 1987.
• 8: Scott F. Woods and Giorgio Casinovi, "A Mixed Digital/Analog Gate-Level Simulation Algorithm", Submitted for publication in IEEE Transactions on Computer-Aided Design.
• 9: C.E. Shannon, "A Symbolic Analysis of Relay and Switching Circuits", Transactions of the American Institute of Electrical Engineers, pp. 713-723, 1938.
• 10: William J. McCalla, Fundamentals of computer-aided circuit simulation, Kluwer, B.V., Deventer, The Netherlands, 1987
• 11: Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
• 12: Karl S. Brace , Richard L. Rudell , Randal E. Bryant, Efficient implementation of a BDD package, Proceedings of the 27th ACM/IEEE conference on Design automation, p.40-45, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123222]
• 13: Melvin A. Breuer and Arthur D. Friedman, Diagnosis & Reliable Design of Digital Systems, Computer Science Press, Inc., Rockville, MD, 1976.
• 14: Giorgio Casinovi and Jeen-Mo Yang, "Multi-Level Simulation of Large Analog Systems Containing Behavioral Models", IEEE Transactions on Computer- AidedDesign, vol. 13, no. 11, pp. 1391-1399,November 1994.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Simulation

General Terms:
Measurement, Performance, Theory, Verification

Keywords:
Gate-level logic simulation, mixed-mode simulation, multi-valued logic, boolean equations solution