| Hybrid decision diagrams |
| Full text |
Publisher Site
,
Pdf
(150 KB)
|
| Source
|
International Conference on Computer Aided Design
archive
Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
table of contents
San Jose, California, United States
Pages: 159 - 163
Year of Publication: 1995
ISBN:0-8186-7213-7
|
|
Authors
|
|
E. M. Clarke
|
School of Computer Science, Carnegie Mellon University, Pittsburgh, PA
|
|
M. Fujita
|
Fujitsu Labs of America Inc., 77 Rio Robles, San Jose, CA
|
|
X. Zhao
|
School of Computer Science, Carnegie Mellon University, Pittsburgh, PA
|
|
| Sponsors |
|
| Publisher |
IEEE Computer Society
Washington, DC, USA
|
| Bibliometrics |
Downloads (6 Weeks): 5, Downloads (12 Months): 13, Citation Count: 26
|
|
|
ABSTRACT
Abstract: Functions that map boolean vectors into the integers are important for the design and verification of arithmetic circuits. MTBDDs and BMDs have been proposed for representing this class of functions. We discuss the relationship between these methods and describe a generalization called hybrid decision diagrams which is often much more concise. We show how to implement arithmetic operations efficiently for hybrid decision diagrams. In practice, this is one of the main limitations of BMDs since performing arithmetic operations on functions expressed in this notation can be very expensive. In order to extend symbolic model checking algorithms to handle arithmetic properties, it is essential to be able to compute the BDD for the set of variable assignments that satisfy an arithmetic relation. In our paper, we give an efficient algorithm for this purpose. Moreover, we prove that for the class of linear expressions, the time complexity of our algorithm is linear in the number of variables.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
R. Iris Bahar , Erica A. Frohm , Charles M. Gaona , Gary D. Hachtel , Enrico Macii , Abelardo Pardo , Fabio Somenzi, Algebraic decision diagrams and their applications, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.188-191, November 07-11, 1993, Santa Clara, California, United States
|
| |
2
|
|
| |
3
|
|
 |
4
|
|
| |
5
|
|
 |
6
|
E. M. Clarke , K. L. McMillan , X Zhao , M. Fujita , J. Yang, Spectral transforms for large boolean functions with applications to technology mapping, Proceedings of the 30th international conference on Design automation, p.54-60, June 14-18, 1993, Dallas, Texas, United States
[doi> 10.1145/157485.164569]
|
 |
7
|
R. Drechsler , A. Sarabi , M. Theobald , B. Becker , M. A. Perkowski, Efficient representation and manipulation of switching functions based on ordered Kronecker functional decision diagrams, Proceedings of the 31st annual conference on Design automation, p.415-419, June 06-10, 1994, San Diego, California, United States
[doi> 10.1145/196244.196444]
|
| |
8
|
|
| |
9
|
D. E. Muller. Application of boolean algebra to switching circuit design and error detection. IRE Trans,, 1:6-12, 1954.
|
CITED BY 26
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
E. M. Clarke , M. Khaira , X. Zhao, Word level model checking—avoiding the Pentium FDIV error, Proceedings of the 33rd annual conference on Design automation, p.645-648, June 03-07, 1996, Las Vegas, Nevada, United States
|
|
|
|
|
|
Christoph Scholl , Bernd Becker , Thomas M. Weis, Word-level decision diagrams, WLCDs and division, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.672-677, November 08-12, 1998, San Jose, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pejman Lotfi-Kamran , Mohammad Hosseinabady , Hamid Shojaei , Mehran Massoumi , Zainalabedin Navabi, TED+: a data structure for microprocessor verification, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
|
|
|
|
|
|
|
|
|
Louis Kruger , Somesh Jha , Eu-Jin Goh , Dan Boneh, Secure function evaluation with ordered binary decision diagrams, Proceedings of the 13th ACM conference on Computer and communications security, October 30-November 03, 2006, Alexandria, Virginia, USA
|
|
|
Vasco Jerinić , Jan Langer , Ulrich Heinkel , Dietmar Müller, New methods and coverage metrics for functional verification, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INDEX TERMS
Primary Classification:
B.
Hardware
B.2
ARITHMETIC AND LOGIC STRUCTURES
General Terms:
Theory
Keywords:
BMDs,
MTBDDs,
arithmetic circuits verification,
binary decision diagrams,
boolean vectors,
circuit analysis computing,
computational complexity,
digital arithmetic,
hybrid decision diagrams,
integers,
linear expressions,
multi-terminal binary decision diagrams,
symbolic model checking algorithms,
time complexity
|