| Bounded-skew clock and Steiner routing under Elmore delay |
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International Conference on Computer Aided Design
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Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
table of contents
San Jose, California, United States
Pages: 66 - 71
Year of Publication: 1995
ISBN:0-8186-7213-7
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Authors
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Jason Cong
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UCLA, Dept. of Computer Science, Los Angeles, CA
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Andrew B. Kahng
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UCLA, Dept. of Computer Science, Los Angeles, CA
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Cheng-Kok Koh
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UCLA, Dept. of Computer Science, Los Angeles, CA
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C.-W. Albert Tsao
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UCLA, Dept. of Computer Science, Los Angeles, CA
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IEEE Computer Society
Washington, DC, USA
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| Bibliometrics |
Downloads (6 Weeks): 1, Downloads (12 Months): 21, Citation Count: 15
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ABSTRACT
We study the minimum-cost bounded-skew routing tree problem under the Elmore delay model. We present two approaches to construct bounded-skew routing trees: (i) the Boundary Merging and Embedding (BME) method which utilizes merging points that are restricted to the boundaries of merging regions, and (ii) the Interior Merging and Embedding (IME) algorithm which employs a sampling strategy and dynamic programming to consider merging points that are interior to, rather than on the boundary of, the merging regions. Our new algorithms allow accurate control of Elmore delay skew, and show the utility of merging points inside merging regions.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength", P1vc. IEEE 5th Intl. ASIC Conf., Rochester, September 1992, pp. 1.1.1 - 1.1.5.
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K. D. Boese, A. B. Kahng, B. A. McCoy and G. Robins, "Near-Optimal Critical Sink Routing Tree Constructions," to appear in IEEE Trans. on CAD, 1995.
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M. Borah, R. M. Owens and M. J. Irwin, "An Edge-Based Heuristic for Rectilinear Steiner Trees", IEEE Trans. on CAD, to appear, Dec. 1994, pp. 1563-1568.
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T.-H. Chao , J.-M. Ho , Y.-C. Hsu, Zero skew clock net routing, Proceedings of the 29th ACM/IEEE conference on Design automation, p.518-523, June 08-12, 1992, Anaheim, California, United States
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T.-H. Chao, Y.-C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero Skew Clock Routing With Minimum Wirelength," IEEE Trans. on Cilvuits and Systems 39(11), Nov. 1992, pp. 799-814.
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J. Cong, A. B. Kahng, C.-K. Koh and C.-W. A. Tsao, "Bounded-Skew Clock and Steiner Routing Under Elmore Delay," UCLA Computer Science Department Technical Report 950030, Aug. 1995.
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J. Cong and C.-K. Koh, "Minimum-Cost Bounded-Skew Clock Routing," P1vc. IEEE Intl. Syrup. on Ci~vuits and Systems, Vol 1, Apr. 1995, pp. 215-218.
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J. Cong and K.-S. Leung, "Optimal Wiresizing Under Elmore Delay Model," IEEE Trans. on Computer-AidedDesign, Mar. 1995, pp. 321-336.
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M. Edahiro, "Minimum Path-Length Equi-Distant Routing," P~vc. IEEE Asia- Pacific Conf. on Cilvuits and Systems, Dec. 1992, pp. 41-46.
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Dennis J. H. Huang , Andrew B. Kahng , Chung-Wen Albert Tsao, On the bounded-skew clock and Steiner routing problems, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.508-513, June 12-16, 1995, San Francisco, California, United States
[doi> 10.1145/217474.217579]
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A. B. Kahng and G. Robins, "A New Class of Iterative Steiner Tree Heuristics with Good Performance", IEEE Transactions on Computer-Aided Design, 11(7), Jul. 1992, pp. 893-902.
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A. B. Kahng and G. Robins, On Optimal Intelvonnectionsfor VLSI, Kluwer Academic Publishers, 1994.
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R.S. Tsay, "An Exact Zero-Skew Clock Routing Algorithm,"IEEE Transactions on Computer-Aided Design, 12(2), Feb. 1993, pp. 242-249.
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CITED BY 15
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I-Min Liu , Tan-Li Chou , Adnan Aziz , D. F. Wong, Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion, Proceedings of the 2000 international symposium on Physical design, p.33-38, May 2000, San Diego, California, United States
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Yehea I. Ismail , Eby G. Friedman , Jose L. Neves, Equivalent Elmore delay for RLC trees, Proceedings of the 36th ACM/IEEE conference on Design automation, p.715-720, June 21-25, 1999, New Orleans, Louisiana, United States
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Atsushi Takahashi , Kazunori Inoue , Yoji Kajitani, Clock-tree routing realizing a clock-schedule for semi-synchronous circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.260-265, November 09-13, 1997, San Jose, California, United States
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INDEX TERMS
Primary Classification:
F.
Theory of Computation
F.2
ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
F.2.2
Nonnumerical Algorithms and Problems
Subjects:
Routing and layout
Additional Classification:
B.
Hardware
B.7
INTEGRATED CIRCUITS
B.7.2
Design Aids
Subjects:
Placement and routing
General Terms:
Algorithms,
Measurement,
Theory
Keywords:
bounded-skew,
zero-skew,
clock routing,
Elmore delay,
pathlength delay,
zero-skew,
VLSI,
routing trees,
global routing
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