Activity-driven clock design for low power circuits

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Activity-driven clock design for low power circuits

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International Conference on Computer Aided Design archive
Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 62 - 65

Year of Publication: 1995

ISBN:0-8186-7213-7

Authors

Gustavo E. Téllez	Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL
Amir Farrahi	Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL
Majid Sarrafzadeh	Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 30, Citation Count: 12

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree can be turned on/off by gating the clock signals during the active/idle times of the clocked elements. We propose a method of obtaining the switching activity patterns of the clocked circuits during the high level design process. We formulate three novel activity-driven problems. The objective of these problems is to minimize system's dynamic power consumption. We propose an approximation algorithm based on recursive matching to solve the clock tree construction problem. We solve the gate insertion problems with an exact algorithm employing the dynamic programming paradigm. Finally, we present experimental results that verify the effectiveness of our approach. Our work in this paper is a step in understanding how high level decisions (e.g. behavioral design) can affect a low level design (e.g. clock design).

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	In International Workshop on Low Power Design, April 1994.
	2	H. B. Bakoglu. "Circuits, Interconnections, and Packaging for VLSI". Addison-Wesley Publishing Co., 1990.
	3	Amir H. Farrahi , Gustavo E. Téllez , Majid Sarrafzadeh, Memory segmentation to exploit sleep mode operation, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.36-41, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217503]
	4	E. G. Friedman. "Clock Distribution Design in VLSI Circuits- an Overview". In International Symposium on Circuits and Systems, pages 1475- 1478, May 1993.
	5	F. Najm. "Transition Density: A New Measure of Activity in Digital Circuits". IEEE Transactions on Computer Aided Design, 12(2):310-323, 1992.
	6	G. T~llez, A. H. Farrahi, and M. Sarrafzadeh. "Activity-Driven Clock Design for Low Power Circuits". Technical report, Northwestern University, EECS Department, Evanston, IL, November 1994.

CITED BY 13

	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Ganesh Lakshminarayana , Anand Raghunathan , Niraj K. Jha , Sujit Dey, Transforming control-flow intensive designs to facilitate power management, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.657-664, November 08-12, 1998, San Jose, California, United States
	Michael J. Alexander, Power optimization for FPGA look-up tables, Proceedings of the 1997 international symposium on Physical design, p.156-162, April 14-16, 1997, Napa Valley, California, United States
	Luca Benini , Giovanni De Micheli, System-level power optimization: techniques and tools, Proceedings of the 1999 international symposium on Low power electronics and design, p.288-293, August 16-17, 1999, San Diego, California, United States
	J. Oh , M. Pedram, Gated clock routing minimizing the switched capacitance, Proceedings of the conference on Design, automation and test in Europe, p.692-697, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Xunwei Wu , Massoud Pedram, Low power sequential circuit design by using priority encoding and clock gating, Proceedings of the 2000 international symposium on Low power electronics and design, p.143-148, July 25-27, 2000, Rapallo, Italy
	Ki-Seok Chung , Taewhan Kim , C. I. Liu, Behavioral-level partitioning for low power design in control-dominated application, Proceedings of the 10th Great Lakes symposium on VLSI, p.156-161, March 02-04, 2000, Chicago, Illinois, United States
	Jumpei Uchida , Nozomu Togawa , Masao Yanagisawa , Tatsuo Ohtsuki, A thread partitioning algorithm in low power high-level synthesis, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.74-79, January 27-30, 2004, Yokohama, Japan
	Azadeh Davoodi , Ankur Srivastava, Voltage scheduling under unpredictabilities: a risk management paradigm, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.354-368, April 2005
	Jo Dale Carothers , Radjakichenin Radjassamy, Low Power VLSI Design Techniques - The Current State, Integrated Computer-Aided Engineering, v.5 n.2, p.153-176, April 1998
	Deniz Dal , Adrian Nunez , Nazanin Mansouri, Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron, Proceedings of the 7th International Symposium on Quality Electronic Design, p.165-170, March 27-29, 2006
	Chia-Ming Chang , Shih-Hsu Huang , Yuan-Kai Ho , Jia-Zong Lin , Hsin-Po Wang , Yu-Sheng Lu, Type-matching clock tree for zero skew clock gating, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Dipanjan Sengupta , Resve A. Saleh, Application-driven voltage-island partitioning for low-power system-on-chip design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.3, p.316-326, March 2009