Generating sparse partial inductance matrices with guaranteed stability

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Generating sparse partial inductance matrices with guaranteed stability

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International Conference on Computer Aided Design archive
Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 45 - 52

Year of Publication: 1995

ISBN:0-8186-7213-7

Authors

Byron Krauter	IBM Corp., 11400 Burnet Road, Austin, TX
Lawrence T. Pileggi	Dept. of Computer and Electrical Engineering, The University of Texas at Austin, Austin, TX and Carnegie Mellon University, Dept. of ECE, Pittsburgh, PA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Washington, DC, USA

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Downloads (6 Weeks): 3, Downloads (12 Months): 16, Citation Count: 34

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ABSTRACT

This paper proposes a definition of magnetic vector potential that can be used to evaluate sparse partial inductance matrices. Unlike the commonly applied procedure of discarding the smallest matrix terms, the proposed approach maintains accuracy at middle and high frequencies and is guaranteed to be positive definite for any degree of sparsity (thereby producing stable circuit solutions). While the proposed technique is strictly based upon potential theory (i.e. the invariance of potential differences on the zero potential reference choice), the technique is, nevertheless, presented and discussed in both circuit and magnetic terms. The conventional and the proposed sparse formulation techniques are contrasted in terms of eigenvalues and circuit simulation results on practical examples.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 34

	Yi-Chang Lu , Mustafa Celik , Tak Young , Lawrence T. Pileggi, Min/max on-chip inductance models and delay metrics, Proceedings of the 38th conference on Design automation, p.341-346, June 2001, Las Vegas, Nevada, United States
	A. J. Dammers , N. P. van der Meijs, Virtual screening: a step towards a sparse partial inductance matrix, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.445-452, November 07-11, 1999, San Jose, California, United States
	Hao Ji , Anirudh Devgan , Wayne Dai, KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect, Proceedings of the 2001 conference on Asia South Pacific design automation, p.379-384, January 2001, Yokohama, Japan
	T. Chen, On the impact of on-chip inductance on signal nets under the influence of power grid noise, Proceedings of the conference on Design, automation and test in Europe, p.451-459, March 2001, Munich, Germany
	Michael W. Beattie , Lawrence T. Pileggi, Modeling magnetic coupling for on-chip interconnect, Proceedings of the 38th conference on Design automation, p.335-340, June 2001, Las Vegas, Nevada, United States
	Kaushik Gala , Vladimir Zolotov , Rajendran Panda , Brian Young , Junfeng Wang , David Blaauw, On-chip inductance modeling and analysis, Proceedings of the 37th conference on Design automation, p.63-68, June 05-09, 2000, Los Angeles, California, United States
	Michael W. Beattie , Lawrence T. Pileggi, IC analyses including extracted inductance models, Proceedings of the 36th ACM/IEEE conference on Design automation, p.915-920, June 21-25, 1999, New Orleans, Louisiana, United States
	Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi, PRIMA: passive reduced-order interconnect macromodeling algorithm, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.58-65, November 09-13, 1997, San Jose, California, United States
	Zhijiang He , Mustafa Celik , Lawrence Pileggi, SPIE: sparse partial inductance extraction, Proceedings of the 34th annual conference on Design automation, p.137-140, June 09-13, 1997, Anaheim, California, United States
	Byron Krauter , Yu Xia , Aykut Dengi , Lawrence T. Pileggi, A sparse image method for BEM capacitance extraction, Proceedings of the 33rd annual conference on Design automation, p.357-362, June 03-07, 1996, Las Vegas, Nevada, United States
	Dipak Sitaram , Yu Zheng , K. L. Shepard, Implicit treatment of substrate and power-ground losses in return-limited inductance extraction, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.16-22, November 10-14, 2002, San Jose, California
	Kaushik Gala , David Blaauw , Junfeng Wang , Vladimir Zolotov , Min Zhao, Inductance 101: analysis and design issues, Proceedings of the 38th conference on Design automation, p.329-334, June 2001, Las Vegas, Nevada, United States
	Guoan Zhong , Cheng-Kok Koh , Kaushik Roy, On-chip interconnect modeling by wire duplication, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.341-346, November 10-14, 2002, San Jose, California
	Haitian Hu , David T. Blaauw , Vladimir Zolotov , Kaushik Gala , Min Zhao , Rajendran Panda , Sachin S. Sapatnekar, A precorrected-FFT method for simulating on-chip inductance, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.221-227, November 10-14, 2002, San Jose, California
	Andrea Pacelli, A local circuit topology for inductive parasitics, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.208-214, November 10-14, 2002, San Jose, California
	Satrajit Gupta , Lawrence T. Pileggi, CHIME: coupled hierarchical inductance model evaluation, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Hao Ji , Qingjian Yu , Wayne Dai, SPICE compatible circuit models for partial reluctance K, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.786-791, January 27-30, 2004, Yokohama, Japan
	Hemant Mahawar , Vivek Sarin , Weiping Shi, A solenoidal basis method for efficient inductance extraction, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Tsung-Hao Chen , Clement Luk , Hyungsuk Kim , Charlie Chung-Ping Chen, INDUCTWISE: inductance-wise interconnect simulator and extractor, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.215-220, November 10-14, 2002, San Jose, California
	Tao Lin , Michael W. Beattie , Lawrence T. Pileggi, On the efficacy of simplified 2D on-chip inductance models, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Hui Zheng , Byron Krauter , Lawrence Pileggi, Electrical Modeling of Integrated-Package Power and Ground Distributions, IEEE Design & Test, v.20 n.3, p.24-31, May 2003
	Michael Beattie , Hui Zheng , Anirudh Devgan , Byron Krauter, Spatially distributed 3D circuit models, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Hui Zheng , Lawrence T. Pileggi, Robust and passive model order reduction for circuits containing susceptance elements, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.761-766, November 10-14, 2002, San Jose, California
	Anirudh Devgan , Hao Ji , Wayne Dai, How to efficiently capture on-chip inductance effects: introducing a new circuit element K, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Hao Yu , Lei He, Vector potential equivalent circuit based on PEEC inversion, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Yu Du , Wayne Dai, Partial reluctance based circuit simulation is efficient and stable, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Tsung-Hao Chen , Clement Luk , Charlie Chung-Ping Chen, SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.786, November 09-13, 2003
	Yu Cao , Xiao-dong Yang , Xuejue Huang , Dennis Sylvester, Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.848, November 09-13, 2003
	Rong Jiang , Charlie Chung-Ping Chen, SCORE: SPICE COmpatible Reluctance Extraction, Proceedings of the conference on Design, automation and test in Europe, p.20948, February 16-20, 2004
	Yuichi Tanji , Takayuki Watanabe , Hideki Asai, Generating stable and sparse reluctance/inductance matrix under insufficient conditions, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Duo Li , Sheldon X.-D. Tan, Hierarchical Krylov subspace reduced order modeling of large RLC circuits, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Kaveh Shakeri , James D. Meindl, Accelerated modeling of massively coupled RLC interconnects using the relative inductance extraction method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.6, p.745-754, June 2008
	Duo Li , Sheldon X. -D. Tan , Lifeng Wu, Hierarchical Krylov subspace based reduction of large interconnects, Integration, the VLSI Journal, v.42 n.2, p.193-202, February, 2009
	Dipanjan Gope , Albert E. Ruehli , Vikram Jandhyala, Speeding Up PEEC partial inductance computations using a QR-based algorithm, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.1, p.60-68, January 2007