Estimation and bounding of energy consumption in burst-mode control circuits

ABSTRACT

This paper describes two techniques to quantify energy consumption of burst-mode asynchronous (clock-less) control circuits. The circuit specifications considered are extended burst-mode specifications, and the implementations are multi-level logic implementations whose outputs are guaranteed to be free of any voltage glitches (hazards). Both techniques use stochastic analysis to combine a small number of simulations in order to quantify average energy per external signal transition. The first technique uses N-valued simulation to derive mathematically tight upper and lower bounds of energy consumption. Using this technique we bound the effect of hazards under all possible operating conditions and environments for a given circuit. Additionally, to drive synthesis tools for low-power, we propose a second technique that uses fixed-delay simulation to derive a realistic estimate of energy consumption within our derived upper and lower bounds. We demonstrate the feasibility of both these techniques on a variety of burst-mode control circuits used in an industrial-quality chip. Our preliminary results indicate that less than 5% of the power of typical multi-level burst-mode circuits can be attributed to hazards.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles

General Terms:
Algorithms, Theory

Keywords:
statistical energy estimation, low power design, asynchronous circuits, hazard-free logic, N-valued simulation