Switching activity analysis using Boolean approximation method

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Switching activity analysis using Boolean approximation method

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International Conference on Computer Aided Design archive
Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 20 - 25

Year of Publication: 1995

ISBN:0-8186-7213-7

Authors

Taku Uchino	Semiconductor DA & Test Engineering Center, Toshiba Corp., 580-1, Horikawa-cho Saiwai-ku Kawasaki 210, Japan
Fumihiro Minami	Semiconductor DA & Test Engineering Center, Toshiba Corp., 580-1, Horikawa-cho Saiwai-ku Kawasaki 210, Japan
Takashi Mitsuhashi	Semiconductor DA & Test Engineering Center, Toshiba Corp., 580-1, Horikawa-cho Saiwai-ku Kawasaki 210, Japan
Nobuyuki Goto	Research and Development Center, Toshiba Corp., 1, Komukai Toshiba-cho Saiwai-ku Kawasaki 210, Japan

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 13, Citation Count: 8

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ABSTRACT

This paper presents a novel algorithm to estimate the signal probability and switching activity at all nodes in a combinational logic circuit under a zero-delay model without constructing global BDDs. By using Taylor expansion technique, the first-order signal correlation effects due to reconvergent fan-out nodes are taken into account. High accuracy is achieved by considering the dependency of the signal probability and switching activity on each primary input. High speed is also achieved by using the incremental approach for probability calculation. Our approach is able to handle large circuits, since it does not need to construct global BDDs for the probability calculation. The analysis of the time complexity and the experimental results show the running time of our approach to be about 100 times shorter than that of the most accurate approach previously proposed and that our approach has comparable accuracy. The error of the total power estimation is about 0.5% on average.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 8

	Taku Uchino , Jason Cong, An interconnect energy model considering coupling effects, Proceedings of the 38th conference on Design automation, p.555-558, June 2001, Las Vegas, Nevada, United States
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, Effects of delay models on peak power estimation of VLSI sequential circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.45-51, November 09-13, 1997, San Jose, California, United States
	Masako Murofushi , Takashi Ishioka , Masami Murakata , Takashi Mitsuhashi, Layout driven re-synthesis for low power consumption LSIs, Proceedings of the 34th annual conference on Design automation, p.666-669, June 09-13, 1997, Anaheim, California, United States
	Dennis J. Ciplickas , Ronald A. Rohrer, Expected current distributions for CMOS circuits, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.589-592, November 10-14, 1996, San Jose, California, United States
	T. Ishihara , H. Yasuura, Basic experimentation on accuracy of power estimation for CMOS VLSI circuits, Proceedings of the 1996 international symposium on Low power electronics and design, p.117-120, August 12-14, 1996, Monterey, California, United States
	T. Uchino , F. Minami , M. Murakata , T. Mitsuhashi, Switching activity analysis for sequential circuits using Boolean approximation method, Proceedings of the 1996 international symposium on Low power electronics and design, p.79-84, August 12-14, 1996, Monterey, California, United States
	José C. Costa , José C. Monteiro , Srinivas Devadas, Switching activity estimation using limited depth reconvergent path analysis, Proceedings of the 1997 international symposium on Low power electronics and design, p.184-189, August 18-20, 1997, Monterey, California, United States