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A scheduling algorithm for multiport memory minimization in datapath synthesis
Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 1995 Asia and South Pacific Design Automation Conference table of contents
Makuhari, Massa, Chiba, Japan
Article No. 16  
Year of Publication: 1995
ISBN:0-89791-766-9
Authors
Hae-Dong Lee
Sun-Young Hwang
Sponsors
IEEE-CAS : Circuits & Systems
IFIP WG 10.2 : IFIP WG 10.2
ISPJ : ISPJ
SIGDA: ACM Special Interest Group on Design Automation
IEICE : Inst of Electronics, Info & Communication Engineers
IFIP WG 10.5 : IFIP WG 10.5
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): n/a,   Downloads (12 Months): n/a,   Citation Count: 6
Additional Information:

cited by   index terms   collaborative colleagues  

Tools and Actions: Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/224818.224847
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CITED BY  6
Youn-Long Lin, Recent developments in high-level synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.1, p.2-21, Jan. 1997
P. R. Panda , F. Catthoor , N. D. Dutt , K. Danckaert , E. Brockmeyer , C. Kulkarni , A. Vandercappelle , P. G. Kjeldsberg, Data and memory optimization techniques for embedded systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.2, p.149-206, April 2001
Shantanu Tarafdar , Miriam Leeser, The DT-model: high-level synthesis using data transfers, Proceedings of the 35th annual conference on Design automation, p.114-121, June 15-19, 1998, San Francisco, California, United States
Jason Cong , Yiping Fan , Wei Jiang, Platform-based resource binding using a distributed register-file microarchitecture, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
Kyoung-Hwan Lim , YongHwan Kim , Taewhan Kim, Interconnect and communication synthesis for distributed register-file microarchitecture, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
Jason Cong , Yiping Fan , Junjuan Xu, Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.14 n.3, p.1-31, May 2009

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Data-path design

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Memory design

  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.2 Nonnumerical Algorithms and Problems
          Subjects: Sequencing and scheduling

  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)


General Terms:
Algorithms, Design

Collaborative Colleagues:
Hae-Dong Lee: colleagues
Sun-Young Hwang: colleagues

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