Power reduction by gate sizing with path-oriented slack calculation

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Power reduction by gate sizing with path-oriented slack calculation

Source

Asia and South Pacific Design Automation Conference archive
Proceedings of the 1995 Asia and South Pacific Design Automation Conference table of contents

Makuhari, Massa, Chiba, Japan

Article No. 2

Year of Publication: 1995

ISBN:0-89791-766-9

Authors

How-Rern Lin
Ting-Ting Hwang

Sponsors

IEEE-CAS : Circuits & Systems
IFIP WG 10.2 : IFIP WG 10.2
ISPJ : ISPJ
SIGDA: ACM Special Interest Group on Design Automation
IEICE : Inst of Electronics, Info & Communication Engineers
IFIP WG 10.5 : IFIP WG 10.5

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 11

Additional Information:

cited by index terms collaborative colleagues

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CITED BY 11

	P. Girard , C. Landrault , S. Pravossoudovitch , D. Severac, A gate resizing technique for high reduction in power consumption, Proceedings of the 1997 international symposium on Low power electronics and design, p.281-286, August 18-20, 1997, Monterey, California, United States
	Masanori Hashimoto , Hidetoshi Onodera , Keikichi Tamaru, A practical gate resizing technique considering glitch reduction for low power design, Proceedings of the 36th ACM/IEEE conference on Design automation, p.446-451, June 21-25, 1999, New Orleans, Louisiana, United States
	Masanori Hashimoto , Hidetoshi Onodera , Keikichi Tamaru, A power optimization method considering glitch reduction by gate sizing, Proceedings of the 1998 international symposium on Low power electronics and design, p.221-226, August 10-12, 1998, Monterey, California, United States
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Chunhong Chen , Majid Sarrafzadeh, Power reduction by simultaneous voltage scaling and gate sizing, Proceedings of the 2000 conference on Asia South Pacific design automation, p.333-338, January 2000, Yokohama, Japan
	Noriyuki Miura , Naoki Kato , Tadahiro Kuroda, Practical methodology of post-layout gate sizing for 15% more power saving, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.434-437, January 27-30, 2004, Yokohama, Japan
	Massoud Pedram , Hirendu Vaishnav, Power Optimization in VLSI Layout: A Survey, Journal of VLSI Signal Processing Systems, v.15 n.3, p.221-232, March 1997
	Chunhong Chen , Xiaojian Yang , Majid Sarrafzadeh, Potential slack: an effective metric of combinational circuit performance, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	S. Ghiasi , E. Bozorgzadeh , S. Choudhuri , M. Sarrafzadeh, A unified theory of timing budget management, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.653-659, November 07-11, 2004
	Soheil Ghiasi , Po-Kuan Huang, Probabilistic Delay Budgeting for Soft Realtime Applications, Proceedings of the 7th International Symposium on Quality Electronic Design, p.141-146, March 27-29, 2006
	Chi-Ming Tsai , Kun-Tien Kuo , Chyi-Hui Hong , Rung-Bin Lin, An Adaptive Interconnect-Length Driven Placer, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.393, January 07-11, 2002