|
|
|
| A data cache with multiple caching strategies tuned to different types of locality |
| Full text |
Pdf
(1.15 MB)
|
| Source
|
International Conference on Supercomputing
archive
Proceedings of the 9th international conference on Supercomputing
table of contents
Barcelona, Spain
Pages: 338 - 347
Year of Publication: 1995
ISBN:0-89791-728-6
|
|
Authors
|
|
Antonio González
|
Universitat Politècnica de Catalunya, Departamento de Arquitectura de Computadores, Campus Nord, Módulo D6, c/ Gran Capitán, s/n, E-08071, Barcelona, Spain
|
|
Carlos Aliagas
|
Universitat Politècnica de Catalunya, Departamento de Arquitectura de Computadores, Campus Nord, Módulo D6, c/ Gran Capitán, s/n, E-08071, Barcelona, Spain
|
|
Mateo Valero
|
Universitat Politècnica de Catalunya, Departamento de Arquitectura de Computadores, Campus Nord, Módulo D6, c/ Gran Capitán, s/n, E-08071, Barcelona, Spain
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 8, Downloads (12 Months): 69, Citation Count: 52
|
|
|
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Santosh G. Abraham , Rabin A. Sugumar , Daniel Windheiser , B. R. Rau , Rajiv Gupta, Predictability of load/store instruction latencies, Proceedings of the 26th annual international symposium on Microarchitecture, p.139-152, December 01-03, 1993, Austin, Texas, United States
|
 |
2
|
|
 |
3
|
|
| |
4
|
|
| |
5
|
A. Chang, Application of Sparse Matrix Methods in Electric Power System Analysis, in Proc. of the Symp. on Sparse Matrices and their Applications, pp. 113-122, 1969,
|
 |
6
|
|
 |
7
|
John W. C. Fu , Janak H. Patel , Bob L. Janssens, Stride directed prefetching in scalar processors, Proceedings of the 25th annual international symposium on Microarchitecture, p.102-110, December 01-04, 1992, Portland, Oregon, United States
|
 |
8
|
|
 |
9
|
|
 |
10
|
|
| |
11
|
G. Kurpanek et al. PA7200. A PA-RISC Processor with Integrated High Performance MP Bus Interface m Proc. of CompCon94, pp. 375-382, 1994,
|
 |
12
|
Monica D. Lam , Edward E. Rothberg , Michael E. Wolf, The cache performance and optimizations of blocked algorithms, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.63-74, April 08-11, 1991, Santa Clara, California, United States
|
 |
13
|
|
 |
14
|
|
| |
15
|
|
 |
16
|
|
| |
17
|
|
 |
18
|
Mateo Valero , Tomás Lang , José M. Llabería , Montse Peiron , Eduard Ayguadé , Juan J. Navarra, Increasing the number of strides for conflict-free vector access, Proceedings of the 19th annual international symposium on Computer architecture, p.372-381, May 19-21, 1992, Queensland, Australia
|
| |
19
|
|
 |
20
|
|
CITED BY 52
|
|
|
|
|
|
|
|
P. R. Panda , F. Catthoor , N. D. Dutt , K. Danckaert , E. Brockmeyer , C. Kulkarni , A. Vandercappelle , P. G. Kjeldsberg, Data and memory optimization techniques for embedded systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.2, p.149-206, April 2001
|
|
|
|
|
|
|
|
|
Jude A. Rivers , Edward S. Tam , Gary S. Tyson , Edward S. Davidson , Matt Farrens, Utilizing reuse information in data cache management, Proceedings of the 12th international conference on Supercomputing, p.449-456, July 1998, Melbourne, Australia
|
|
|
|
|
|
|
|
|
S. Kim , N. Vijaykrishnan , M. Kandemir , A. Sivasubramaniam , M. J. Irwin , E. Geethanjali, Power-aware partitioned cache architectures, Proceedings of the 2001 international symposium on Low power electronics and design, p.64-67, August 2001, Huntington Beach, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Teresa L. Johnson , Matthew C. Merten , Wen-Mei W. Hwu, Run-time spatial locality detection and optimization, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.57-64, December 01-03, 1997, Research Triangle Park, North Carolina, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Aviral Shrivastava , Ilya Issenin , Nikil Dutt, Compilation techniques for energy reduction in horizontally partitioned cache architectures, Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, September 24-27, 2005, San Francisco, California, USA
|
|
|
|
|
|
|
|
|
|
|
|
Ning An , Sudhanva Gurumurthi , Anand Sivasubramaniam , Narayanan Vijaykrishnan , Mahmut Kandemir , Mary Jane Irwin, Energy-performance trade-offs for spatial access methods on memory-resident data, The VLDB Journal — The International Journal on Very Large Data Bases, v.11 n.3, p.179-197, November 2002
|
|
|
|
|
|
Kyoungwoo Lee , Aviral Shrivastava , Ilya Issenin , Nikil Dutt , Nalini Venkatasubramanian, Mitigating soft error failures for multimedia applications by selective data protection, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, October 22-25, 2006, Seoul, Korea
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|