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ABSTRACT
Abstract: In this paper we briefly describe a set of designs that earn serve as examples for high level synthesis (HLS) systems. The designs vary in complexity from simple behavioral finite state machines to more complex designs such as microprocessors and floating point units. Most of the designs are described in the VHDL language at the behavioral level. We divide the designs into two categories. The first category contains designs that have documentation on the specifications of the designs along with the strategy used to test the individual design models. The second category contains examples used in many HLS papers, but lack comprehensive documentation and/or test vectors.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 22
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H. Tomiyama , T. Ishihara , A. Inoue , H. Yasuura, Instruction scheduling for power reduction in processor-based system design, Proceedings of the conference on Design, automation and test in Europe, p.855-860, February 23-26, 1998, Le Palais des Congrés de Paris, France
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K. S. Khouri , G. Lakshminarayana , N. K. Jha, IMPACT: a high-level synthesis system for low power control-flow intensive circuits, Proceedings of the conference on Design, automation and test in Europe, p.848-854, February 23-26, 1998, Le Palais des Congrés de Paris, France
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Indradeep Ghosh , Niraj K. Jha , Sudipta Bhawmik, A BIST scheme for RTL controller-data paths based on symbolic testability analysis, Proceedings of the 35th annual conference on Design automation, p.554-559, June 15-19, 1998, San Francisco, California, United States
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Indradeep Ghosh , Sujit Dey , Niraj K. Jha, A fast and low cost testing technique for core-based system-on-chip, Proceedings of the 35th annual conference on Design automation, p.542-547, June 15-19, 1998, San Francisco, California, United States
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Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau, Exploiting off-chip memory access modes in high-level synthesis, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.333-340, November 09-13, 1997, San Jose, California, United States
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Youngsoo Shin , Soo-IK Chae , Kiyoung Choi, Partial bus-invert coding for power optimization of system level bus, Proceedings of the 1998 international symposium on Low power electronics and design, p.127-129, August 10-12, 1998, Monterey, California, United States
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INDEX TERMS
Primary Classification:
C.
Computer Systems Organization
C.0
GENERAL
Subjects:
Systems specification methodology
Additional Classification:
B.
Hardware
B.6
LOGIC DESIGN
B.6.3
Design Aids
Subjects:
Hardware description languages
Nouns:
VHDL
General Terms:
Design,
Documentation,
Languages,
Measurement,
Verification
Keywords:
1995 high level synthesis design repository,
VHDL language,
behavioral finite state machines,
behavioral level,
computational complexity,
finite state machines,
floating point units,
hardware description languages,
high level synthesis,
microprocessor chips,
microprocessors
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