Power analysis and low-power scheduling techniques for embedded DSP software

ABSTRACT

Abstract: This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been developed using this technique. Significant points of difference have been observed between this model and the ones developed earlier for some general-purpose commercial microprocessors. In particular, the effect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the DSP processor has a special architectural feature that allows instructions to be packed into pairs. The energy reduction possible through the use of this feature is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A micro-architectural power model for the multiplier is developed and analyzed for further energy minimization. A scheduling algorithm incorporating these new techniques is proposed to reduce the energy consumed by DSP software. Energy reductions varying from 11% to 56% have been observed for several example programs. These energy savings are real and have been verified through physical measurement.

REFERENCES

• 1: Vivek Tiwari , Sharad Malik , Andrew Wolfe, Power analysis of embedded software: a first step towards software power minimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.437-445, Dec. 1994 [doi>10.1109/92.335012]
• 2: Vivek Tiwari , Mike Tien-Chien Lee, Power analysis of a 32-bit embedded microcontroller, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.23-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan [doi>10.1145/224818.224890]
• 3: V. Tiwari, S. Malik, and A. Wolfe. "Compilation techniques for low energy: An overview". In Proc. Syrup. on Low Power Electronics, Oct. 1994.
• 4: Ching-Long Su , Chi-Ying Tsui , Alvin M. Despain, Saving Power in the Control Path of Embedded Processors, IEEE Design & Test, v.11 n.4, p.24-30, October 1994 [doi>10.1109/54.329448]
• 5: Mike T.-C. Lee, V. Tiwari, S. Malik, and M. Fujita. "Power analysis and low-power scheduling techniques for embedded DSP software". Technical Report FLA- CTM-02, Fujitsu Labs. of America, 1995.
• 6: Kai Hwang, Computer Arithmetic: Principles, Architecture and Design, John Wiley & Sons, Inc., New York, NY, 1979
• 7: Mike Johnson. Superscalar Microprocessor Design, chapter 10. Basic Software Scheduling. Prentice Hall, 1990.
• 8: Texas Instruments. Digital Signal Processing Applications- Theory, Algorithm, and Implementations. 1986.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.4 Performance Analysis and Design Aids**
          Subjects: Formal models**

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Arithmetic and logic units

General Terms:
Algorithms, Measurement, Performance

Keywords:
DSP processor, application specific integrated circuits, circuit CAD, circuit state, digital signal processing chips, embedded DSP software, energy consumption, energy minimization, energy reduction, general-purpose commercial microprocessors, instruction sets, instruction-level power model, low-power scheduling, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, power analysis, real-time systems, scheduling, scheduling algorithm