Scheduling and resource binding for low power

ABSTRACT

Abstract: Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during the scheduling and resource-binding steps of high-level synthesis. Algorithms for these steps targeting at low-power data-paths and trading off, in some cases, speed and area for low power are presented. The algorithms focus on reducing the activity of the functional units (adders, multipliers) by minimizing the transitions of their input operands. The power consumption of the functional units accounts for a large fraction of the overall data-path power budget.

REFERENCES

• 1: C. Wayne Brown , Barry J. Shepherd, Graphics file formats: reference and guide, Manning Publications Co., Greenwich, CT, 1995
• 2: T. D. Burd , R. W. Brodersen, Energy efficient CMOS microprocessor design, Proceedings of the 28th Hawaii International Conference on System Sciences (HICSS'95), p.288, January 04-07, 1995
• 3: A. Chandrakasan, M. Potkonjak, J. Rabaey, and R. Brodersen. HYPER-LP: A system for power minimization using architectural transformations. IEEE Trans. on CAD, pages 300-303, Nov. 1992.
• 4: A. Chandrakasan, S. Sheng, and R. Broderssen. Low power CMOS digital design. IEEE Trans. on SSC, 27(4):473-483, Apr. 1992.
• 5: A. Chatterjee and R. Roy. Synthesis of low power linear DSP circuits using activity metrics. In Proc. of the Int. Conf. on VLSI Design, pages 265-270, Jan. 1994.
• 6: Diana Marculescu , Radu Marculescu , Massoud Pedram, Information theoretic measures of energy consumption at register transfer level, Proceedings of the 1995 international symposium on Low power design, p.81-86, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224096]
• 7: Aurobindo Dasgupta , Ramesh Karri, Simultaneous scheduling and binding for power minimization during microarchitecture synthesis, Proceedings of the 1995 international symposium on Low power design, p.69-74, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224094]
• 8: E Dewilde, E. Deprettere, and R. Nouta. Parallel and pipelined VLSI implementation of signal processing algorithms, chapter 15, pages 257-264. VLSI and Modem Signal Processing. Prentice-Hall, Inglewood Cliffs, NJ, 1985.
• 9: Daniel D. Gajski , Nikil D. Dutt , Allen C.-H. Wu , Steve Y.-L. Lin, High-level synthesis: introduction to chip and system design, Kluwer Academic Publishers, Norwell, MA, 1992
• 10: Israel Koren, Computer arithmetic algorithms, Prentice-Hall, Inc., Upper Saddle River, NJ, 1993
• 11: S. Kung. On supercomputing with systolic/wavefront array processor. In Proc. of the IEEE, pages 867-884, July 1984.
• 12: E Landman and J. Rabaey. Black-box capacitance models for architectural power analysis. In Proc. Int. Workshop on Low Power Desi~,n, pages 165-170, Apr. 1994.
• 13: Paul E. Landman , Jan M. Rabaey, Activity-sensitive architectural power analysis for the control path, Proceedings of the 1995 international symposium on Low power design, p.93-98, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224098]
• 14: E. Musoll , J. Cortadella, High-level synthesis techniques for reducing the activity of functional units, Proceedings of the 1995 international symposium on Low power design, p.99-104, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224099]
• 15: Farid N. Najm, Towards a high-level power estimation capability, Proceedings of the 1995 international symposium on Low power design, p.87-92, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224097]
• 16: William H. Press , Saul A. Teukolsky , William T. Vetterling , Brian P. Flannery, Numerical recipes in C (2nd ed.): the art of scientific computing, Cambridge University Press, New York, NY, 1992
• 17: Anand Raghunathan , Niraj K. Jha, Behavioral Synthesis for low Power, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.318-322, October 10-12, 1994
• 18: K. Rao and E Yip. Discrete Cosine Transform. Academic Press, 1990.
• 19: John R. Treichler , C. Richard Johnson, Jr. , Michael J. Larimore, Theory and design of adaptive filters, Wiley-Interscience, New York, NY, 1987
• 20: A. van Gerenden. SLS: An efficient switch-level timing simulator using rain-max voltage waveforms. In Proc. VLSI 89 Conf., pages 79-88, Aug. 1989.
• 21: S. Wuytack,-F. Catthoor, F~. Franseen, L. Nachtergaele, and H. D. Man. Global communications and memory optimizing transformations for low power. In Proc. Int. Workshop on Low Power Design, pages 203-208, Apr. 1994.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Arithmetic and logic units
      B.5.2 Design Aids
          Subjects: Optimization

General Terms:
Algorithms, Design, Performance

Keywords:
adders, data flow graphs, data-path power budget, functional units, high level synthesis, high-level synthesis, logic circuits, low power, low-power data-paths, multipliers, network synthesis, power consumption, resource binding, resource-binding, scheduling, trading off