Multiple-process behavioral synthesis for mixed hardware-software systems

ABSTRACT

Abstract: Systems composed of microprocessors interacting with ASICs are necessarily multiple-process systems, since the controller in the microprocessor is separate from any controllers on the ASIC. For this reason, the design of such systems offers an opportunity to exploit not only hardware-software tradeoffs, but concurrency tradeoffs as well. The paper describes an automated iterative improvement technique for performing concurrency optimization and hardware-software tradeoffs simultaneously. Experimental results illustrate that addressing these two issues simultaneously enables us to identify a number of interesting cost/performance points that would not have been found otherwise.

REFERENCES

• 1: W. Wolf and R. Manno, "High-Level Modeling and Synthesis of Communicating Processes Using VHDL," IEICE Trans. on Information and Systems, vol. E76-D, no. 9, pp. 1039-46, 1995.
• 2: Petru Eles , Marius Minea , Krzysztof Kuchcinski , Zebo Peng, Synthesis of VHDL concurrent processes, Proceedings of the conference on European design automation, p.540-545, September 19-23, 1994, Grenoble, France
• 3: R. A. Walker and D. E. Thomas, "Design representation and transformation in The System Architect's Workbench," in Proceedings: ICCAD-87, 1987.
• 4: John William Hagerman, Synthesis of multiple process digital systems, Carnegie Mellon University, Pittsburgh, PA, 1995
• 5: T. B. Ismail, K. O'Brien, and A. Jerraya, "Interactive System-Level Partitioning with PARTIF," in Proceedings of EURO-DAC/EURO-VHDL '94, 1994.
• 6: Jörg Henkel , Rolf Ernst , Ullrich Holtmann , Thomas Benner, Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.96-100, November 06-10, 1994, San Jose, California, United States
• 7: Rajesh K. Gupta , Giovanni De Micheli, Hardware-Software Cosynthesis for Digital Systems, IEEE Design & Test, v.10 n.3, p.29-41, July 1993 [doi>10.1109/54.232470]
• 8: D. D. Gajski, F. Vahid, and S. Narayan, "A system-design methodology: executable-specification refinement," in Proceedings: ED&T Conference, 1994.
• 9: Donald E. Thomas , Jay K. Adams , Herman Schmit, A Model and Methodology for Hardware-Software Codesign, IEEE Design & Test, v.10 n.3, p.6-15, July 1993 [doi>10.1109/54.232468]
• 10: Frank Vahid , Daniel D. Gajski, Incremental hardware estimation during hardware/software functional partitioning, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.3, p.459-464, Sept. 1995 [doi>10.1109/92.407006]
• 11: Jay K. Adams , John Alan Miller , Donald E. Thomas, Execution-time profiling for multiple-process behavioral synthesis, Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors, p.144-149, October 02-04, 1995
• 12: W. Ye, R. Ernst, T. Benner, and J. Henkel, "Fast Timing Analysis for Hardware-Software Co-Synthesis," in Proceedings: ICCD-93, 1993.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

          Nouns: ASIC

Additional Classification:
  D. Software
  D.2 SOFTWARE ENGINEERING
      D.2.8 Metrics
          Subjects: Performance measures

  G. Mathematics of Computing
  G.1 NUMERICAL ANALYSIS

General Terms:
Design, Experimentation, Languages, Performance

Keywords:
ASICs, application specific integrated circuits, automated iterative improvement technique, concurrency control, concurrency optimization, concurrency tradeoffs, controllers, cost-benefit analysis, cost/performance ratio, hardware-software tradeoffs, high level synthesis, logic design, microprocessor chips, microprocessors, mixed hardware-software systems, multiple-process behavioral synthesis, multiprocessing systems, optimisation, resource allocation, software engineering