Multiway netlist partitioning onto FPGA-based board architecture

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Multiway netlist partitioning onto FPGA-based board architecture

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European Design Automation Conference archive
Proceedings of the conference on European design automation table of contents

Brighton, England

Pages: 150 - 155

Year of Publication: 1995

ISBN:0-8186-7156-4

Authors

U. Ober	Institute of Microelectronic Systems, Darmstadt University of Technology, Karlstr. 15, 64283 Darmstadt, Germany
M. Glesner	Institute of Microelectronic Systems, Darmstadt University of Technology, Karlstr. 15, 64283 Darmstadt, Germany

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 10, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
	2	B.W. Kernighan, S. Lin: An Efficient Heuristic Procedure for Partitioning Graphs; Bell System Technical Journal, 49:291-307, 1970.
	3	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Papers on Twenty-five years of electronic design automation, p.241-247, June 1988 [doi>10.1145/62882.62910]
	4	C. Kring, A. R. Newton: A Cell Replicating Approach to Mincut-Based Circuit Partitioning; Proc. IEEE International Conference on Computer-Aided Design, Santa Clara, California, November 1991.
	5	S.W. Hadley, B. L. Mark, A. Vannelli: An Efficient Eigenvector Approach for Finding Netlist Partitions; IEEE Transactions on Computer-Aided Design, 11(7):885-892, July 1992.
	6	L. Hagen, A. Kahng: Fast Spectral Methods for Ratio Cut Partitioning and Clustering; Proc. IEEE International Conference on Computer-Aided Design, Santa Clara, California, November 1991.
	7	J. Cong , L. Hagen , A. Kahng, Net partitions yield better module partitions, Proceedings of the 29th ACM/IEEE conference on Design automation, p.47-52, June 08-12, 1992, Anaheim, California, United States
	8	M.R. Green, J. Supowit: Simulated Annealing without Rejected Moves; Digest International Conference on Computer Design, pp 658-663, October 1984.
	9	R. Kuznar, F. Brglez, K. Kozminski: Partitioning Digital Circuits for Implementation in Multiple FPGA ICs; Technical Report, MCNC Center for Mikroelectronic Systems Technologies, March 8, 1993.
	10	Roman Kužnar , Franc Brglez , Krzysztof Kozminski, Cost minimization of partitions into multiple devices, Proceedings of the 30th international conference on Design automation, p.315-320, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164910]
	11	H. J. Herpel, N. Wehn, M. Gasteier, M. Glesner: A Reconfigurable Computer for Embedded Control Applications; IEEE Workshop on FPGAs for Custom Computing Machines, Napa, California, April 5-7, 1993.
	12	J. Babb, R. Tessier, A. Agarwal: Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators; IEEE Workshop on FPGAs for Custom Computing Machines, Napa, California, April 5-7, 1993.
	13	C. Iseli, E. Sanchez: Spyder: A Reconfigurable VLIW Processor using FPGAs; IEEE Workshop on FPGAs for Custom Computing Machines, Napa, California, April 5-7, 1993.
	14	P.W. Foulk: Data-folding in SRAM configurable FPGAs; IEEE Workshop on FPGAs for Custom Computing Machines, Napa, California, 1993.