Testable synthesis of high complex control devices

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Testable synthesis of high complex control devices

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European Design Automation Conference archive
Proceedings of the conference on European design automation table of contents

Brighton, England

Pages: 117 - 122

Year of Publication: 1995

ISBN:0-8186-7156-4

Authors

F. Fummi	Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy
U. Rovati	Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy
D. Sciuto	Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 0, Citation Count: 4

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Hideo Fujiwara, Logic testing and design for testability, Massachusetts Institute of Technology, Cambridge, MA, 1985
	2	S.Yang, "Logic Synthesis and Optimization Benchmarks User Guide", Technical Report Microelectronic Center of North Carolina, 1991.
	3	EFummi, "The Tetstability Design of High Complex Circuits", Ph.D. Thesis, Dept. of Electronic and Information, Politecnico di Milano, 1995.
	4	Franco Fummi , Donatella Sciuto , Micaela Serra, Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: A Mixed Functional/Structural Method, Proceedings of the The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, p.254-262, October 17-19, 1994
	5	F. Fummi , D. Sciuto , M. Serra, Sequential logic minimization based on functional testability, Proceedings of the 1995 European conference on Design and Test, p.207, March 06-09, 1995
	6	C.Bolchini, EFummi, D.Sciuto, "Two-Dimensional Sequential Array Architectures: Design for Testability and Reconfiguration Issues", Journal of Microelectronic Systems Integration, Vol. 1, No, 3/4. pp.209-220, 1993.
	7	Design and Test of Computers, vo1.12, n.1, 1995.
	8	V. D. Agrawal , K.-T. Cheng, Finite state machine synthesis with embedded test function, Journal of Electronic Testing: Theory and Applications, v.1 n.3, p.221-228, Oct. 1990
	9	S.T.Chakradhar, S.Kanjilal, V.D. Agrawal, "Finite State Machine Synthesis with Fault Tolerant Test Function", Journal of Electronic Testing: Theory and Applications, vol.4, pp.57-69, 1993.
	10	Suman Kanjilal , Srimat T. Chakradhar , Vishwani D. Agrawal, A Synthesis Approach to Design for Testability, Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them, p.754-763, October 17-21, 1993
	11	S.Kanjilal, S.T.Chakradhar, V.D. Agrawal, "Test Function Embedding Algorithms with Application to Interconnected Finite State Machines", Proc. EDAC/ETC, 1993.

CITED BY 4

	Irith Pomeranz , Sudhakar M. Reddy, On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines, IEEE Transactions on Computers, v.49 n.1, p.88-94, January 2000
	F. Fummi , U. Rovati , D. Sciuto, Functional design for testability of control-dominated architectures, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.2, p.98-122, April 1997
	I. Pomeranz , S. M. Reddy, On the use of reset to increase the testability of interconnected finite-state machines, Proceedings of the 1997 European conference on Design and Test, p.554, March 17-20, 1997
	Irith Pomeranz , Sudhakar M. Reddy, On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem, Proceedings of the 1996 European conference on Design and Test, p.380, March 11-14, 1996