On generating compact test sequences for synchronous sequential circuits

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On generating compact test sequences for synchronous sequential circuits

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European Design Automation Conference archive
Proceedings of the conference on European design automation table of contents

Brighton, England

Pages: 105 - 110

Year of Publication: 1995

ISBN:0-8186-7156-4

Authors

Irith Pomeranz	Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA
Sudhakar M. Reddy	Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 4, Citation Count: 11

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	I. Pomeranz, L.N. Reddy and S.M. Reddy, "COMPACTEST: A Method To Generate Compact Test Sets for Combinational Circuits", IEEE Trans. on CAD, July 1993, pp. 1040-1049.
	2	Gert-Jan Tromp, Minimal Test Sets for Combinatorial Circuits, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.204-209, October 26-30, 1991
	3	M. Abramovici , K. B. Rajan , D. T. Miller, Freeze!: a new approach for testing sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.22-25, June 08-12, 1992, Anaheim, California, United States
	4	R.K. Roy, T. M. Niermann, J. H. Patel, J. A. Abraham and R. A. Saleh, "Compaction of ATPG-Generated Test Sequences for Sequential Circuits", in Proc. Intl. Conf. on Computer-Aided Design, Nov. 1988, pp. 382-385.
	5	M. Abramovici, J.J. Kulikowski, P.R. Menon and D.T. Miller, "SMART and FAST: Test Generation for VLSI Scan-Design Circuits," IEEE Design and Test of Comp., August 1986, pp. 43-54.
	6	V.D. Agrawal, K. T. Cheng, and P. Agrawal, "A Directed Search Method for Test Generation Using Concurrent Simulator", IEEE Trans. CAD of ICS, February 1989, pp. 131-138.
	7	T.P. Kelsey and K. K. Saluja, "Fast Test Generation for Sequential Circuits", Intl. Conf. Comp. Aided Design, Nov. 1989, pp. 354-357.
	8	I. Pomeranz and S.M. Reddy, "Test Generation for Synchronous Sequential Circuits Based on Fault Extraction", 1991 Intl. Conf. on Computer-Aided Design, Nov. 1991, pp. 450-453.
	9	H. Cho, G. D. Hachtel and F. Somenzi, "Redundancy Identification/Removal and Test Generation for Sequential Circuits Using Implicit State Enumeration", IEEE Trans. on CAD, July 1993, pp. 935-945.
	10	Thomas Niermann , Janak H. Patel, HITEC: a test generation package for sequential circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	11	D.-H. Lee and S. M. Reddy, "A New Test Generation Method for Sequential Circuits", 1991 Intl. Conf. on Computer-Aided Design, Nov. 1991, pp. 446-449.
	12	Elizabeth M. Rudnick , Janak H. Patel , Gary S. Greenstein , Thomas M. Niermann, Sequential circuit test generation in a genetic algorithm framework, Proceedings of the 31st annual conference on Design automation, p.698-704, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196619]
	13	I. Pomeranz , S. M. Reddy, Classification of Faults in Synchronous Sequential Circuits, IEEE Transactions on Computers, v.42 n.9, p.1066-1077, September 1993 [doi>10.1109/12.241596]
	14	Irith Pomeranz , Sudhakar M. Reddy, On achieving a complete fault coverage for sequential machines using the transition fault model, Proceedings of the 28th conference on ACM/IEEE design automation, p.341-346, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127691]

CITED BY 11

	Srimat T. Chakradhar , Anand Raghunathan, Bottleneck removal algorithm for dynamic compaction and test cycles reduction, Proceedings of the conference on European design automation, p.98-104, September 18-22, 1995, Brighton, England
	Anand Raghunathan , Srimat T. Chakradhar, Acceleration techniques for dynamic vector compaction, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.310-317, November 05-09, 1995, San Jose, California, United States
	Irith Pomeranz , Sudhakar M. Reddy, On static compaction of test sequences for synchronous sequential circuits, Proceedings of the 33rd annual conference on Design automation, p.215-220, June 03-07, 1996, Las Vegas, Nevada, United States
	Elizabeth M. Rudnick , Janak H. Patel, Simulation-based techniques for dynamic test sequence compaction, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.67-73, November 10-14, 1996, San Jose, California, United States
	Irith Pomeranz , Sudhakar M. Reddy, ITEM: an iterative improvement test generation procedure for synchronous sequential circuits, Proceedings of the 11th Great Lakes symposium on VLSI, p.13-18, March 2001, West Lafayette, Indiana, United States
	Irith Pomeranz , Sudhakar M. Reddy, Built-in generation of weighted test sequences for synchronous sequential circuits, Proceedings of the conference on Design, automation and test in Europe, p.298-304, March 27-30, 2000, Paris, France
	Elizabeth M. Rudnick , Janak H. Patel, Efficient Techniques for Dynamic Test Sequence Compaction, IEEE Transactions on Computers, v.48 n.3, p.323-330, March 1999
	Irith Pomeranz , Sudhakar M. Reddy, Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits, IEEE Transactions on Computers, v.49 n.6, p.596-607, June 2000
	Irith Pomeranz , Sudhakar M. Reddy, On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits, IEEE Transactions on Computers, v.49 n.2, p.175-182, February 2000
	Yanti Santoso , Matthew Merten , Elizabeth M. Rudnick , Miron Abramovici, FreezeFrame: compact test generation using a frozen clock strategy, Proceedings of the conference on Design, automation and test in Europe, p.147-es, January 1999, Munich, Germany
	Irith Pomeranz , Sudhakar M. Reddy, On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem, Proceedings of the 1996 European conference on Design and Test, p.380, March 11-14, 1996