Bottleneck removal algorithm for dynamic compaction and test cycles reduction

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. H. Schulz, E. Trischler, and T. M. Sarfert, "SOCRATES: A Highly Efficient Automatic Test Pattern Generation System," IEEE Trans. Computer-AidedDesign, vol. 7, pp. 126-136,Jan. 1988.
	2	L. N. Reddy, I. Pomeranz, and S. M. Reddy, "ROTCO: A Reverse Order Test Compaction Technique," in Proc. EURO-ASIC Conf., pp. 189-194, Sept. 1992.
	3	S. Kajihara, I. Pomeranz, K. Kinoshita, and S. M. Reddy, "On Compacting Test Sets by Addition and Removal of Test Vectors," in VLSI Test Syrup., pp. 202-207, Apr. 1994.
	4	Prabhakar Goel , Barry C. Rosales, PODEM-X: An automatic test generation system for VLSI logic structures, Proceedings of the 18th conference on Design automation, p.260-268, June 29-July 01, 1981, Nashville, Tennessee, United States
	5	Seiji Kajihara , Irith Pomeranz , Kozo Kinoshita , Sudhakar M. Reddy, Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits, Proceedings of the 30th international conference on Design automation, p.102-106, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164617]
	6	Sridhar Narayanan , Rajesh Gupta , Melvin Breuer, Configuring multiple scan chains for minimum test time, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.4-8, November 1992, Santa Clara, California, United States
	7	B. Vinnakota and N. K. Jha, "Synthesis of Sequential Circuits for Parallel Scan," in P1vc. Eulvpean Design Automation Conf., pp. 366-370, Mar. 1992.
	8	D. K. Pradhan and J. Saxena, "A Design for Testability Scheme to Reduce Test Application Time in Full Scan," in P~vc. VLSI Test Syrup., pp. 55-60, Apr. 1992.
	9	E. M. Rudnick , J. H. Patel, A genetic approach to test application time reduction for full scan and partial scan circuits, Proceedings of the 8th International Conference on VLSI Design, p.288, January 04-07, 1995
	10	Yoshinobu Higami , Seiji Kajihara , Kozo Kinoshita, Reduced Scan Shift: A New Testing Method for Sequential Circuit, Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years, p.624-630, October 02-06, 1994
	11	T. M. Niermann, R. K. Roy, J. H. Patel, and J. A. Abraham, "Test Compaction for Sequential Circuits," IEEE Trans. Computer-Aided Design, vol. 11, pp. 260-267, Feb. 1992.
	12	S. Y. Lee and K. K. Saluja, "Sequential Test Generation with Reduced Test Clocks for Partial Scan Designs," in P~vc. VLSI Test Syrup., pp. 220-225, April 1994.
	13	Irith Pomeranz , Sudhakar M. Reddy, On generating compact test sequences for synchronous sequential circuits, Proceedings of the conference on European design automation, p.105-110, September 18-22, 1995, Brighton, England
	14	S. T. Chakradhar, V. D. Agrawal, and S. Rothweiler, "A Transitive Closure Algorithm for Test Generation," IEEE Trans. Computer-Aided Design, vol. 12, pp. 1015-1028, July 1993.
	15	X. Chen and M. L. Bushnell, "Dynamic State and Objective Learning for Sequential Circuit Test Generation Using Decomposition Equivalence," in P~vc. of the 24th Int. Syrup. Fault Tolerant Comput., pp. 446-455,June 1994.