Exploiting power-up delay for sequential optimization

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Exploiting power-up delay for sequential optimization

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European Design Automation Conference archive
Proceedings of the conference on European design automation table of contents

Brighton, England

Pages: 54 - 59

Year of Publication: 1995

ISBN:0-8186-7156-4

Authors

Vigyan Singhal	Cedence Berkeley Labs, 1919 Addison St., Berkelcy, CA
Carl Pixley	Motorola Inc., Bridgepoint Plaza I. 5918 W. Courtyard Dr., Suite 200, Austin, TX
Adnan Aziz	Department of EECS, University of California, Berkeley, CA
Robert K. Brayton	Department of EECS, University of California, Berkeley, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 3, Citation Count: 6

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	C. Pixley, "A Theory and Implementation of Sequential Hardware Equivalence," IEEE Trans. Computer-Aided Design, vol. 11, pp. 1469-1494, Dec. 1992.
	2	Vigyan Singhal , Carl Pixley, The Verifiacation Problem for Safe Replaceability, Proceedings of the 6th International Conference on Computer Aided Verification, p.311-323, June 21-23, 1994
	3	I. Pomeranz , S. M. Reddy, Classification of Faults in Synchronous Sequential Circuits, IEEE Transactions on Computers, v.42 n.9, p.1066-1077, September 1993 [doi>10.1109/12.241596]
	4	Carl Pixley , Vigyan Singhal , Adnan Aziz , Robert K. Brayton, Multi-level synthesis for safe replaceability, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.442-449, November 06-10, 1994, San Jose, California, United States
	5	Seh-Woong Jeong, Binary decision diagrams and their applications to implicit enumeration techniques in logic synthesis, University of Colorado at Boulder, Boulder, CO, 1992
	6	Vigyan Singhal , Carl Pixley , Richard L. Rudell , Robert K. Brayton, The validity of retiming sequential circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.316-321, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217548]
	7	K.-T. Cheng, "Redundancy Removal for Sequential Circuits Without Reset States," IEEE Trans. Computer-Aided Design, vol. 12, pp. 13-24, Jan. 1993.
	8	Luis Entrena , Kwang-Ting Cheng, Sequential logic optimization by redundancy addition and removal, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.310-315, November 07-11, 1993, Santa Clara, California, United States
	9	M. A. Iyer, D. E. Long, and M. Abramovici, "Identifying Sequential Redundancies Without Search." Unpublished manuscript, 1995.
	10	S. Malik, E. M. Sentovich, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Retiming and Resynthesis: Optimization of Sequential Networks with Combinational Techniques" IEEE Trans. Computer-Aided Design, vol. 10, pp. 74-84, Jan. 1991.
	11	C. E. Leiserson and J. B. Saxe, "Optimizing Synchronous Systems," Journal of VLSI and Computer Systems, vol. 1, pp. 41-67, Spring 1983.
	12	M. Damiani , G. De Micheli, Recurrence equations and the optimization of synchronous logic circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.556-561, June 08-12, 1992, Anaheim, California, United States
	13	V. Singhal, C. Pixley, A. Aziz, and R. K. Brayton, "Delaying Safeness for More Flexibility," Tech. Rep. UCB/ERL M95/5, Electronics Research Lab, Univ. of California, Berkeley, CA 94720, Jan. 1995.
	14	Adnan Aziz , Thomas R. Shiple , Vigyan Singhal, Formula-Dependent Equivalence for Compositional CTL Model Checking, Proceedings of the 6th International Conference on Computer Aided Verification, p.324-337, June 21-23, 1994
	15	H. Savoj and R. K. Brayton, "Observability Relations and Observability Don't Cares," in Proc. Intl. Conf. on Computer- Aided Design, (Santa Clara, CA), pp. 518-521, Nov. 1991.
	16	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	17	H. Savoj, R. K. Brayton, and H. Touati, "Extracting Local Don't Cares for Network Optimization," in Proc. Intl. Conf. on Computer-Aided Design, (Santa Clara, CA), pp. 514-517, Nov. 1991.

CITED BY 6

	Q. Wang , S. B. K. Vrudhula, Data driven power optimization of sequential circuits, Proceedings of the conference on Design, automation and test in Europe, p.686-691, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Vigyan Singhal , Sharad Malik , Robert K. Brayton, The case for retiming with explicit reset circuitry, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.618-625, November 10-14, 1996, San Jose, California, United States
	Mahesh A. Iyer , David E. Long , Miron Abramovici, Identifying sequential redundancies without search, Proceedings of the 33rd annual conference on Design automation, p.457-462, June 03-07, 1996, Las Vegas, Nevada, United States
	A. Mehrotra , S. Qadeer , V. Singhal , R. K. Brayton , A. Aziz , A. L. Sangiovanni-Vincentelli, Sequential optimisation without state space exploration, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.208-215, November 09-13, 1997, San Jose, California, United States
	Vigyan Singhal , Carl Pixley , Adnan Aziz , Shaz Qadeer , Robert Brayton, Sequential optimization in the absence of global reset, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.2, p.222-251, April 2003
	Irith Pomeranz , Sudhakar M. Reddy, Functional broadside tests under an expanded definition of functional operation conditions, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.1, p.121-129, January 2009