Timing optimization by bit-level arithmetic transformations

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Timing optimization by bit-level arithmetic transformations

Full text

Pdf (594 KB)

Source

European Design Automation Conference archive
Proceedings of the conference on European design automation table of contents

Brighton, England

Pages: 48 - 53

Year of Publication: 1995

ISBN:0-8186-7156-4

Authors

Luc Rijnders	IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Zohair Sahraoui	IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Paul Six	IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Hugo De Man	Katholieke Universiteit Leuven and IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 3, Citation Count: 1

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A.D. Booth : "A Signed Binary Multiplication Algorithm", Quarterly Journal of Mechanics and Applied Mathematics, pp. 236-240, 1951.
	2	C.S. Wallace : "A suggestion for a fast multiplier", IEEE Trans. Electron. Comput., pp. 14-17, Feb. 1964.
	3	L. Dadda : "Some schemes for parallel multipliers", Alta Frequenza, pp, 349-356, 1965.
	4	C. Leiserson, J. Saxe : "Optimizing Synchronous Circuitry by Retiming", Third Caltech Conference on VLSI, Computer Science Press, 1983.
	5	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	6	K.J. Singh, et al. : "Timing optimization of combinational logic", IEEE Int. Conf. on Computer-Aided Design, pp. 282-285, 1988.
	7	S. Note, et al. : "Combined Hardware Selection and Pipelining in High-Performance Data-Path Design", IEEE Int. Conf. on Comp. Design, pp. 328-331, 1990.
	8	John P. Fishburn, A depth-decreasing heuristic for combinational logic: or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between, Proceedings of the 27th ACM/IEEE conference on Design automation, p.361-364, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123305]
	9	H.R. Srinivas, K.K. Parhi : "A Fast VLSI Adder Architecture", IEEE Journal of Solid-State Circuits, pp. 761-767, May 1992.
	10	Zhi-Jian (Alex) Mou , Francis Jutand, 'Overturned-Stairs' Adder Trees and Multiplier Design, IEEE Transactions on Computers, v.41 n.8, p.940-948, August 1992 [doi>10.1109/12.156536]