A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes

Full text

Pdf (686 KB)

Source

European Design Automation Conference archive
Proceedings of the conference on European design automation table of contents

Brighton, England

Pages: 8 - 13

Year of Publication: 1995

ISBN:0-8186-7156-4

Authors

M. Schwiegershausen	University of Hannover, Laboratorium für Informationstechnologie, Schneiderberg 32, 30167 Hannover, Germany
P. Pirsch	University of Hannover, Laboratorium für Informationstechnologie, Schneiderberg 32, 30167 Hannover, Germany

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 7, Citation Count: 3

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	W. Rosenstiel, H. Krgmer, "Scheduling and Assignment in High Level Synthesis", in High Level VLSI Synthesis, R. Composano, W. Wolf, editors, Kluwer Academic Publishers, pp. 355-382, 1991.
	2	S.Y. Kung, S.N. Jean, "A VLSI Array Compiler System (VACS) for Array Design", R.W. Brodersen, H.S. Moscovitz, editors, VLSI Signal Processing III, Chapter 45, pp. 495 - 508, IEEE Press, New York, 1988.
	3	J. Rabbaey, H. de Man, J. Vanhoof, G. Goosens, F. Cathoor, "CATHEDRAL II: A Synthesis System for Multiprocessor DSP Systems", in Silicon Compilation, Addison-Wesley, pp. 311-360, 1988.
	4	Jan Vanhoof , Ivo Bolsens , Karl Van Rompaey , Gert Goossens , Hug De Man, High-Level Synthesis for Real-Time Digital Signal Processing, Kluwer Academic Publishers, Norwell, MA, 1993
	5	A. Bachmann, M. SchSbinger, L. Thiele, "Synthesis for Domain-Specific Multiprocessor Systems including Memory Design", L.D.J. Eggermont, P. Dewilde, E. Depettre, J. van Meerbergen, editors, VLSI Signal Processing VI, Part 3, pp. 417-425, IEEE Press, New York, 1993.
	6	S. Prakash, A.C. Parker, "Synthesis of Application Specific Heterogeneous Multiprocessor Systems", Journal of Parallel and Distributed Computing, no. 16, pp. 338 - 351, December 1992.
	7	CCITT Study Group XV: Recommendation H.261, "Video Codec for Audiovisual Services at p x 64 kbit/s, Report R37, Geneva, July 1990.

CITED BY 3

	Robert P. Dick , Niraj K. Jha, MOCSYN: multiobjective core-based single-chip system synthesis, Proceedings of the conference on Design, automation and test in Europe, p.55-es, January 1999, Munich, Germany
	Lech Jówiak , Sien-An Ong, Quality-driven model-based architecture synthesis for real-time embedded SoCs, Journal of Systems Architecture: the EUROMICRO Journal, v.54 n.3-4, p.349-368, March, 2008
	Haris Javaid , Sri Parameswaran, Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study, Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, October 19-24, 2008, Atlanta, GA, USA