| Detecting coarse-grain parallelism using an interprocedural parallelizing compiler |
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Conference on High Performance Networking and Computing
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Proceedings of the 1995 ACM/IEEE conference on Supercomputing (CDROM)
table of contents
San Diego, California, United States
Article No. 49
Year of Publication: 1995
ISBN:0-89791-816-9
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Authors
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Mary H. Hall
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Computer Systems Laboratory, Stanford University, Stanford, CA and Computer Science Dept., California Institute of Technology, Pasadena, CA
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Saman P. Amarasinghe
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Computer Systems Laboratory, Stanford University, Stanford, CA and Computer Science Dept., California Institute of Technology, Pasadena, CA
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Brian R. Murphy
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Computer Systems Laboratory, Stanford University, Stanford, CA and Computer Science Dept., California Institute of Technology, Pasadena, CA
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Shih-Wei Liao
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Computer Systems Laboratory, Stanford University, Stanford, CA and Computer Science Dept., California Institute of Technology, Pasadena, CA
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Monica S. Lam
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Computer Systems Laboratory, Stanford University, Stanford, CA and Computer Science Dept., California Institute of Technology, Pasadena, CA
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Downloads (6 Weeks): 4, Downloads (12 Months): 31, Citation Count: 40
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ABSTRACT
This paper presents an extensive empirical evaluation of an interprocedural parallelizing compiler, developed as part of the Stanford SUIF compiler system. The system incorporates a comprehensive and integrated collection of analyses, including privatization and reduction recognition for both array and scalar variables, and symbolic analysis of array subscripts. The interprocedural analysis framework is designed to provide analysis results nearly as precise as full inlining but without its associated costs. Experimentation with this system shows that it is capable of detecting coarser granularity of parallelism than previously possible. Specifically, it can parallelize loops that span numerous procedures and hundreds of lines of codes, frequently requiring modifications to array data structures such as privatization and reduction transformations. Measurements from several standard benchmark suites demonstrate that an integrated combination of interprocedural analyses can substantially advance the capability of automatic parallelization technology.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Jennifer M. Anderson , Saman P. Amarasinghe , Monica S. Lam, Data and computation transformations for multiprocessors, Proceedings of the fifth ACM SIGPLAN symposium on Principles and practice of parallel programming, p.166-178, July 19-21, 1995, Santa Barbara, California, United States
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M. W. Hall, S. Amarasinghe, and B. Murphy. Interprocedural analysis for parallelization: Design and experience. In Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing, pages 650-655, San Francisco, CA, February 1995.
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CITED BY 40
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E. Gutiérrez , O. Plata , E. L. Zapata, A compiler method for the parallel execution of irregular reductions in scalable shared memory multiprocessors, Proceedings of the 14th international conference on Supercomputing, p.78-87, May 08-11, 2000, Santa Fe, New Mexico, United States
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Shih-Wei Liao , Amer Diwan , Robert P. Bosch, Jr. , Anwar Ghuloum , Monica S. Lam, SUIF Explorer: an interactive and interprocedural parallelizer, ACM SIGPLAN Notices, v.34 n.8, p.37-48, Aug. 1999
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Michael Beynon , Chialin Chang , Umit Catalyurek , Tahsin Kurc , Alan Sussman , Henrique Andrade , Renato Ferreira , Joel Saltz, Processing large-scale multi-dimensional data in parallel and distributed environments, Parallel Computing, v.28 n.5, p.827-859, May 2002
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Saman P. Amarasinghe , Jennifer M. Anderson , Christopher S. Wilson , Shih-Wei Liao , Brian R. Murphy , Robert S. French , Monica S. Lam , Mary W. Hall, Multiprocessors from a Software Perspective, IEEE Micro, v.16 n.3, p.52-61, June 1996
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Mary W. Hall , Jennifer M. Anderson , Saman P. Amarasinghe , Brian R. Murphy , Shih-Wei Liao , Edouard Bugnion , Monica S. Lam, Maximizing Multiprocessor Performance with the SUIF Compiler, Computer, v.29 n.12, p.84-89, December 1996
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Silvius Rus , Guobin He , Christophe Alias , Lawrence Rauchwerger, Region array SSA, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
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J. Ceng , J. Castrillon , W. Sheng , H. Scharwächter , R. Leupers , G. Ascheid , H. Meyr , T. Isshiki , H. Kunieda, MAPS: an integrated framework for MPSoC application parallelization, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
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Andrea Marongiu , Luca Benini , Mahmut Kandemir, Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, September 30-October 03, 2007, Salzburg, Austria
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Mohammad Zalfany Urfianto , Tsuyoshi Isshiki , Arif Ullah Khan , Dongju Li , Hiroaki Kunieda, Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E91-A n.7, p.1748-1756, July 2008
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