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Detecting coarse-grain parallelism using an interprocedural parallelizing compiler
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Source Conference on High Performance Networking and Computing archive
Proceedings of the 1995 ACM/IEEE conference on Supercomputing (CDROM) table of contents
San Diego, California, United States
Article No. 49  
Year of Publication: 1995
ISBN:0-89791-816-9
Authors
Mary H. Hall  Computer Systems Laboratory, Stanford University, Stanford, CA and Computer Science Dept., California Institute of Technology, Pasadena, CA
Saman P. Amarasinghe  Computer Systems Laboratory, Stanford University, Stanford, CA and Computer Science Dept., California Institute of Technology, Pasadena, CA
Brian R. Murphy  Computer Systems Laboratory, Stanford University, Stanford, CA and Computer Science Dept., California Institute of Technology, Pasadena, CA
Shih-Wei Liao  Computer Systems Laboratory, Stanford University, Stanford, CA and Computer Science Dept., California Institute of Technology, Pasadena, CA
Monica S. Lam  Computer Systems Laboratory, Stanford University, Stanford, CA and Computer Science Dept., California Institute of Technology, Pasadena, CA
Sponsors
IEEE-CS : Computer Society
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 31,   Citation Count: 40
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ABSTRACT

This paper presents an extensive empirical evaluation of an interprocedural parallelizing compiler, developed as part of the Stanford SUIF compiler system. The system incorporates a comprehensive and integrated collection of analyses, including privatization and reduction recognition for both array and scalar variables, and symbolic analysis of array subscripts. The interprocedural analysis framework is designed to provide analysis results nearly as precise as full inlining but without its associated costs. Experimentation with this system shows that it is capable of detecting coarser granularity of parallelism than previously possible. Specifically, it can parallelize loops that span numerous procedures and hundreds of lines of codes, frequently requiring modifications to array data structures such as privatization and reduction transformations. Measurements from several standard benchmark suites demonstrate that an integrated combination of interprocedural analyses can substantially advance the capability of automatic parallelization technology.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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K. Cooper, M.W. Hall, and K. Kennedy. A methodology for procedure cloning. Computer Languages, 19(2), April 1993.
 
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M. W. Hall, S. Amarasinghe, and B. Murphy. Interprocedural analysis for parallelization: Design and experience. In Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing, pages 650-655, San Francisco, CA, February 1995.
 
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F. Irigoin. Interprocedural analyses for programming environments. In NSF- CNRS Workshop on Evironments and Tools for Parallel Scientific Programming, September 1992.
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R. Metzger and P. Smith. The CONVEX application compiler. Fortran Journal, 3(1):8-10, 1991.
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J. P. Singh and J. L. Hennessy. An empirical investigation of the effectiveness of and limitations of automatic parallelization. In Proceedings of the International Symposium on Shared Memory Multiprocessors, Tokyo, Japan, April 1991.
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CITED BY  40

Collaborative Colleagues:
Mary H. Hall: colleagues
Saman P. Amarasinghe: colleagues
Brian R. Murphy: colleagues
Shih-Wei Liao: colleagues
Monica S. Lam: colleagues