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An estimation technique to guide low power resynthesis algorithms
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents
Dana Point, California, United States
Pages: 227 - 232  
Year of Publication: 1995
ISBN:0-89791-744-8
Authors
Christopher K. Lennard  Department of EECS, U.C. Berkeley
A. Richard Newton  Department of EECS, U.C. Berkeley
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 7,   Citation Count: 3
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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C.K. Lennard. "Estimation Techniques to Guide Resynthesis for Low-Power on Random Combinational CMOS Logic Networks." PhD Thesis, U.C. Berkeley, to be submitted May 1995.
 
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C.K. Lennard. "Resynthesis Techniques for Power Optimization of Combinational Random Logic Circuits." PhD Thesis Qualifying Proposal Presentation, U.C. Berkeley, Dec. 1993.
 
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B. Lin and H. De Man. "Low-Power Driven Technology Mapping under Timing Constraints." In P1vceedings of the Int' l Workshop on Logic Synthesis (IWLS-93), May 1993.
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Collaborative Colleagues:
Christopher K. Lennard: colleagues
A. Richard Newton: colleagues