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Guarded evaluation: pushing power management to logic synthesis/design

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 221 - 226

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

Vivek Tiwari	Dept. of Electrical Engineering, Princeton Univ.
Sharad Malik	Dept. of Electrical Engineering, Princeton Univ.
Pranav Ashar	C&C Research Labs., NEC

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 36, Citation Count: 25

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Mazhar Alidina , José Monteiro , Srinivas Devadas , Abhijit Ghosh , Marios Papaefthymiou, Precomputation-based sequential logic optimization for low power, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.426-436, Dec. 1994 [doi>10.1109/92.335011]
	2	L. Benini, R Siegel, and G. De Micheli. Automatic synthesis of gated-clocks for power reduction in sequential circuits. IEEE Design and Test, December 1994.
	3	L. Berman and L. Trevillyan. Global flow optimization in automatic logic design. IEEE Transactions on Computer-aided design, 10(5), May 1991.
	4	R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. MIS: A Multiple-Level Logic Optimization System. In IEEE Transactions on Computer-Aided Design, pages 1062-1081, November 1987.
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	6	A. Ghosh , S. Devadas , K. Keutzer , J. White, Estimation of average switching activity in combinational and sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.253-259, June 08-12, 1992, Anaheim, California, United States
	7	Amelia Shen , Abhijit Ghosh , Srinivas Devadas , Kurt Keutzer, On average power dissipation and random pattern testability of CMOS combinational logic networks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.402-407, November 1992, Santa Clara, California, United States
	8	U. Ko, R Balsara, and W. Lee. A self-timed method to minimize spurious transitions in low power CMOS circuits. In Proceedings of the 1994 IEEE Workshop on Low Power Electronics, October 1994.
	9	Wolfgang Kunz , Prem R. Menon, Multi-level logic optimization by implication analysis, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.6-13, November 06-10, 1994, San Jose, California, United States
	10	C. Lemonds and S. S. Shetti. A low power 16 by 16 multiplier using transition reduction circuitry. In Proceedings of the 1994 Intl. Workshop on Low Power Design, pages 139-142, April 1994.
	11	Farid N. Najm, Transition density, a stochastic measure of activity in digital circuits, Proceedings of the 28th conference on ACM/IEEE design automation, p.644-649, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127744]
	12	Vivek Tiwari , Pranav Ashar , Sharad Malik, Technology mapping for lower power, Proceedings of the 30th international conference on Design automation, p.74-79, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164581]

CITED BY 25

	Mitsuhisa Ohnishi , Akihisa Yamada , Hiroaki Noda , Takashi Kambe, A method of redundant clocking detection and power reduction at RT level design, Proceedings of the 1997 international symposium on Low power electronics and design, p.131-136, August 18-20, 1997, Monterey, California, United States
	Ki-Seok Chung , C. L. Liu, Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction, Proceedings of the 1998 international symposium on Low power electronics and design, p.215-220, August 10-12, 1998, Monterey, California, United States
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Ganesh Lakshminarayana , Anand Raghunathan , Niraj K. Jha , Sujit Dey, Transforming control-flow intensive designs to facilitate power management, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.657-664, November 08-12, 1998, San Jose, California, United States
	Luca Benini , Alessandro Bogliolo , Giovanni De Micheli, A survey of design techniques for system-level dynamic power management, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
	Jason J. Brown , Danny Z. Chen , Garrison W. Greenwood , Xiaobo Hu , Richard W. Taylor, Scheduling for power reduction in a real-time system, Proceedings of the 1997 international symposium on Low power electronics and design, p.84-87, August 18-20, 1997, Monterey, California, United States
	José C. Monteiro , Arlindo L. Oliveira, FSM decomposition by direct circuit manipulation applied to low power design, Proceedings of the 2000 conference on Asia South Pacific design automation, p.351-358, January 2000, Yokohama, Japan
	Emil Talpes , Diana Marculescu, Power reduction through work reuse, Proceedings of the 2001 international symposium on Low power electronics and design, p.340-345, August 2001, Huntington Beach, California, United States
	Qi Wang , Sarma B. K. Vrudhula , Gary Yeap , Shantanu Ganguly, Power reduction and power-delay trade-offs using logic transformations, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.1, p.97-121, Jan. 1999
	José Monteiro , Srinivas Devadas , Pranav Ashar , Ashutosh Mauskar, Scheduling techniques to enable power management, Proceedings of the 33rd annual conference on Design automation, p.349-352, June 03-07, 1996, Las Vegas, Nevada, United States
	Anand Raghunathan , Sujit Dey , Niraj K. Jha , Kazutoshi Wakabayashi, Power management techniques for control-flow intensive designs, Proceedings of the 34th annual conference on Design automation, p.429-434, June 09-13, 1997, Anaheim, California, United States
	Srinivas Devadas , Sharad Malik, A survey of optimization techniques targeting low power VLSI circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.242-247, June 12-16, 1995, San Francisco, California, United States
	Qi Wang , Sarma B. K. Vrudhula, Multi-level logic optimization for low power using local logic transformations, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.270-277, November 10-14, 1996, San Jose, California, United States
	Enrico Macii , Massoud Pedram , Fabio Somenzi, High-level power modeling, estimation, and optimization, Proceedings of the 34th annual conference on Design automation, p.504-511, June 09-13, 1997, Anaheim, California, United States
	Emil Talpes , Diana Marculescu, Execution cache-based microarchitecture power-efficient superscalar processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.1, p.14-26, January 2005
	Steve Haga , Natasha Reeves , Rajeev Barua , Diana Marculescu, Dynamic functional unit assignment for low power, The Journal of Supercomputing, v.31 n.1, p.47-62, January 2005
	Vasily G. Moshnyaga, Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits, Journal of VLSI Signal Processing Systems, v.33 n.1, p.75-8, January-February 2003
	A. Chattopadhyay , B. Geukes , D. Kammler , E. M. Witte , O. Schliebusch , H. Ishebabi , R. Leupers , G. Ascheid , H. Meyr, Automatic ADL-based operand isolation for embedded processors, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Vinod Viswanath , Jacob A. Abraham , Warren A. Hunt, Jr, Automatic insertion of low power annotations in RTL for pipelined microprocessors, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Enoch Hwang , Frank Vahid , Yu-Chin Hsu, FSMD functional partitioning for low power, Proceedings of the conference on Design, automation and test in Europe, p.7-es, January 1999, Munich, Germany
	L. Benini , G. De Micheli , A. Macii , E. Macii , M. Poncino , R. Scarsi, Glitch power minimization by gate freezing, Proceedings of the conference on Design, automation and test in Europe, p.36-es, January 1999, Munich, Germany
	Steve Haga , Natasha Reeves , Rajeev Barua , Diana Marculescu, Dynamic Functional Unit Assignment for Low Power, Proceedings of the conference on Design, Automation and Test in Europe, p.11052, March 03-07, 2003
	P. Surti , L. F. Chao , A. Tyagi, Low power FSM design using Huffman-style encoding, Proceedings of the 1997 European conference on Design and Test, p.521, March 17-20, 1997
	M. Favalli , L. Benini , G. de Micheli, Design for Testability of Gated-Clock FSMs, Proceedings of the 1996 European conference on Design and Test, p.589, March 11-14, 1996
	Yu-Min Kuo , Shih-Hung Weng , Shih-Chieh Chang, A novel sequential circuit optimization with clock gating logic, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California