2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits

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2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 191 - 196

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

A. Kramer	AT&T Bell Laboratories, Holmdel, NJ
J. S. Denker	AT&T Bell Laboratories, Holmdel, NJ
B. Flower	AT&T Bell Laboratories, Holmdel, NJ
J. Moroney	AT&T Bell Laboratories, Holmdel, NJ

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 41, Citation Count: 13

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Rolf Landauer, "Irreversibility and Heat Generation in the Computing Process", IBM J. Res. Devel. vol. 5 pp. 183-191 (1961).
	2	C.H. Bennett, "Logical Reversibility of Computation", IBM J. Res. Devel. vol. 17, pp525-532 (1973).
	3	C. Seitz et al., "Hot Clock nMOS", Proceedings of the 1985 Chapel Hill Conference on VLSI. Computer Science Press (1985).
	4	Roderick T. Hinman and Martin F. Schlecht, "Power Dissipation Measurements on Recovered Energy Logic", 1994 Symposium on VLSI Circuits / Digest of Technical Papers, 19. IEEE (June 1994).
	5	A. G. Dickinson and J. S. Denker, "Adiabatic Dynamic Logic", Proceedings of the Custom Integrated Circuits Conference. IEEE (1994).
	6	J. G. Koller and W.C. Athas, "Adiabatic Switching, Low Energy Computing, and the Physics of Storing and Erasing Information", PhysComp '92: Proc. of the Workshop on Physics and Computation. IEEE (1993).
	7	Ralph C. Merkle, "Reversible Electronic Logic using Switches", Nanotechnology Vol. 4 21-40. (1993).
	8	Alan Kramer, John S. Denker, Stephen C. Avery, Alex G. Dickinson, and Thomas R. Wik, "Adiabatic Computing with the 2N-2N2D Logic Family", 1994 Symposium on VLSI Circuits / Digest of Technical Papers, 25. IEEE (June 1994).
	9	J. S. Hall, "An Electroid Switching Model for Reversible Computer Architectures", PhysComp '92: Proc. of the Workshop on Physics and Computation. IEEE (1993).
	10	Saed G. Younis , Thomas F. Knight, Jr., Practical implementation of charge recovering asymptotically zero power CMOS, Proceeding of the 1993 symposium on Research on integrated systems, p.234-250, February 1993, Seattle, Washington, United States
	11	T.J. Gabara, "Pulsed Low Power CMOS", Inter. J. of High Speed Elec. and Systems, Vol. 5 2, (1994).

CITED BY 13

	Suhwan Kim , Marios C. Papaefthymiou, Single-phase source-coupled adiabatic logic, Proceedings of the 1999 international symposium on Low power electronics and design, p.97-99, August 16-17, 1999, San Diego, California, United States
	Suhwan Kim , Marios C. Papaefthymiou, True single-phase energy-recovering logic for low-power, high-speed VLSI, Proceedings of the 1998 international symposium on Low power electronics and design, p.167-172, August 10-12, 1998, Monterey, California, United States
	Suhwan Kim , Conrad H. Ziesler , Marios C. Papaefthymiou, A true single-phase 8-bit adiabatic multiplier, Proceedings of the 38th conference on Design automation, p.758-763, June 2001, Las Vegas, Nevada, United States
	Massoud Pedram , Xunwei Wu, Analysis of power-clocked CMOS with application to the design of energy-recovery circuits, Proceedings of the 2000 conference on Asia South Pacific design automation, p.339-344, January 2000, Yokohama, Japan
	Suhwan Kim , Conrad H. Ziesler , Marios C. Papaefthymiou, A true single-phase energy-recovery multiplier, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.2, p.194-207, April 2003
	D. Frank, Comparison of high speed voltage-scaled conventional and adiabatic circuits, Proceedings of the 1996 international symposium on Low power electronics and design, p.377-380, August 12-14, 1996, Monterey, California, United States
	Visvesh Sathe , Juang-Ying Chueh , Joohee Kim , Conrad H. Ziesler , Suhwan Kim , Marios C. Papaefthymiou, Fast, efficient, recovering, and irreversible, Proceedings of the 2nd conference on Computing frontiers, May 04-06, 2005, Ischia, Italy
	Suhwan Kim , Conrad H. Ziesler , Marios C. Papaefthymiou, Charge-Recovery Computing on Silicon, IEEE Transactions on Computers, v.54 n.6, p.651-659, June 2005
	Guoqiang Hang, Adiabatic CMOS gate and adiabatic circuit design for low-power applications, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Anand Paul , A. Ebenezer Jeyakumar , P. N. Neelakantan , K. John Pratheep, Energy recovery strategy for low power CMOS circuits design, Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing, p.1-5, December 07-09, 2003, Singapore
	Micah C. Knapp , Peter J. Kindlmann , Marios C. Papaefthymiou, Design and Evaluation of Adiabatic Arithmetic Units, Analog Integrated Circuits and Signal Processing, v.14 n.1-2, p.71-79, Sept. 1997
	Mehrdad Khatir , Amir Moradi , Alireza Ejlali , Mohammad T. Manzuri Shalmani , Mahmoud Salmasizadeh, A secure and low-energy logic style using charge recovery approach, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
	Jianping Hu , Dong Zhou , Ling Wang , Huiying Dong, Low-power interface circuits between adiabatic and standard CMOS circuits, Analog Integrated Circuits and Signal Processing, v.60 n.1-2, p.105-115, August 2009