Optimization of power dissipation and skew sensitivity in clock buffer synthesis

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Optimization of power dissipation and skew sensitivity in clock buffer synthesis

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 179 - 184

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

Jae W. Chung	Department of Computer Science and Engineering, Mail Code 0114, University of California, San Diego, La Jolla, California
De-Yu Kao	Department of Electrical and Computer Engineering, Mail Code 0407, University of California, San Diego, La Jolla, California
Chung-Kuan Cheng	Department of Computer Science and Engineering, Mail Code 0114, University of California, San Diego, La Jolla, California
Ting-Ting Lin	Department of Electrical and Computer Engineering, Mail Code 0407, University of California, San Diego, La Jolla, California

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

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Downloads (6 Weeks): 1, Downloads (12 Months): 17, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H. Bakoglu, "Circuits, Interconnections and Packaging for VLSI," Addison-Wesley, 1990.
	2	K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees with Minimum Wire-length," Proc. 5th IEEE Intl. Conf on ASIC, NY, pp. 17 - 21, 1992.
	3	T.-H. Chao , J.-M. Ho , Y.-C. Hsu, Zero skew clock net routing, Proceedings of the 29th ACM/IEEE conference on Design automation, p.518-523, June 08-12, 1992, Anaheim, California, United States
	4	N.-C. Chou and C.-K. Cheng, "Wire Length and Delay Minimization in General Clock Net Routing," Proc. IEEE Intl. Conf. on Computer-Aided Design, pp. 552- 555, 1993.
	5	Jason Cong , Cheng-Kok Koh, Simultaneous driver and wire sizing for performance and power optimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.408-425, Dec. 1994 [doi>10.1109/92.335010]
	6	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
	7	Jae Chung , Chung-Kuan Cheng, Skew sensitivity minimization of buffered clock tree, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.280-283, November 06-10, 1994, San Jose, California, United States
	8	Masato Edahiro, An efficient zero-skew routing algorithm, Proceedings of the 31st annual conference on Design automation, p.375-380, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196426]
	9	B. Hoppe, G. Neuendorf, D. Schmitt-Landsiedel, and W. Specks, "Optimization of High-Speed CMOS Logic Circuits with Analytical Models for Signal Delay, Chip Area, and Dynamic Power Dissipation," IEEE Transactions on Computer Aided Design, vol 9. no. 3., March 1990.
	10	Michael A. B. Jackson , Arvind Srinivasan , E. S. Kuh, Clock routing for high-performance ICs, Proceedings of the 27th ACM/IEEE conference on Design automation, p.573-579, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123406]
	11	Andrew Kahng , Jason Cong , Gabriel Robins, High-performance clock routing based on recursive geometric matching, Proceedings of the 28th conference on ACM/IEEE design automation, p.322-327, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127688]
	12	Shen Lin , C. K. Wong, Process-variation-tolerant clock skew minimization, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.284-288, November 06-10, 1994, San Jose, California, United States
	13	T. Sakurai, "A Unified Theory for Mixed CMOS/ B iCMOS Buffer Optimization," IEEE Journal of Solid- State Circuits, vol. 27, no. 7, July 1992.
	14	R.-S. Tsay, "Exact Zero Skew," Proc. IEEE Intl. Conf. on Computer Aided Design, pp. 336-339, 1991.
	15	Neil H. E. Weste , Kamran Eshraghian, Principles of CMOS VLSI design: a systems perspective, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985