Power and area optimization by reorganizing CMOS complex gate circuits

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Power and area optimization by reorganizing CMOS complex gate circuits

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 155 - 160

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

M. Tachibana	Research Laboratory 1, ULSI Research Laboratories, R&D Center, Toshiba Corp.
S. Kurosawa	Research Laboratory 1, ULSI Research Laboratories, R&D Center, Toshiba Corp.
R. Nojima	Research Laboratory 1, ULSI Research Laboratories, R&D Center, Toshiba Corp.
N. Kojima	Research Laboratory 1, ULSI Research Laboratories, R&D Center, Toshiba Corp.
M. Yamada	Research Laboratory 1, ULSI Research Laboratories, R&D Center, Toshiba Corp.
T. Mitsuhashi	Research Laboratory 1, ULSI Research Laboratories, R&D Center, Toshiba Corp.
N. Goto	Research Laboratory 1, ULSI Research Laboratories, R&D Center, Toshiba Corp.

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

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Downloads (6 Weeks): 7, Downloads (12 Months): 15, Citation Count: 0

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REFERENCES

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