Techniques for fast circuit simulation applied to power estimation of CMOS circuits

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Techniques for fast circuit simulation applied to power estimation of CMOS circuits

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 135 - 138

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

Premal Buch	University of California, Berkeley, CA
Shen Lin	IBM T. J. Watson Research Center, Yorktown Heights, NY
Vijay Nagasamy	LSI Logic Corporation, Milpitas, CA
Ernest S. Kuh	University of California, Berkeley, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 27, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. R Chandrakashan, S. Sheng and R. Brodersen, "Low Power CMOS Digital Design," IEEE Transactions on Solid-State Circuits, Vol. 27, No. 4, pp. 473-483, April 1992.
	2	M. A. Cirit, "Estimating Dynamic Power Consumption of CMOS Circuits," IEEE International Conference on Computer-Aided Design, pp. 534-537, Nov. 1987.
	3	A.-C. Deng, "Power Analysis for CMOS/BiCMOS Circuits," Proceedings of the International Workshop on Low Power Design, 1994.
	4	HSPICE Version H92 User's Manual, Meta-Software Inc., Campbell, CA.
	5	S. M. Kang, "Accurate Estimation of Power Dissipation in VLSI Circuits," IEEE Journal of Solid-State Circuits, Vol. SC- 21, pp. 889-891, Oct. 1986.
	6	K. Keutzer and E Vanbekbergen, "The Impact of CAD on the Design of Low Power Digital Circuits" In Proceedings of the 1994 IEEE Symposium on Low Power Electronics, pp 42-45, San Diego, CA, Oct 10-12, 1994.
	7	E E. Landman and J. M. Rabaey, "Power Estimation for High Level Synthesis", Proceedings of EDAC-EUROASIC '93, Paris, France, pp. 361-366, February 1993
	8	S. Lin, E. S. Kuh, and M. Marek-Sadowska, "Stepwise Equivalent Conductance Circuit Simulation Technique", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 5, pp. 672-683, May 1993.
	9	F. Najm, "Estimating Power Dissipation in VLSI Circuits", Technical Report, University of Illinois at Urbana-Champaign, May 1994.
	10	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Efficient estimation of dynamic power consumption under a real delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.224-228, November 07-11, 1993, Santa Clara, California, United States

CITED BY 2

	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	S. Huang , K. Cheng , K. Chen , T. Lee, A novel methodology for transistor-level power estimation, Proceedings of the 1996 international symposium on Low power electronics and design, p.67-72, August 12-14, 1996, Monterey, California, United States