High-level synthesis techniques for reducing the activity of functional units

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High-level synthesis techniques for reducing the activity of functional units

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 99 - 104

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

E. Musoll	Department of Computer Architecture, Universitat Politècnica de Catalunya, 08071-Barcelona, Spain
J. Cortadella	Department of Computer Architecture, Universitat Politècnica de Catalunya, 08071-Barcelona, Spain

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 33, Citation Count: 24

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	K. Masselos , S. Theoharis , P. K. Merakos , T. Stouraitis , C. E. Goutis, Low power synthesis of sum-of-products computation (poster session), Proceedings of the 2000 international symposium on Low power electronics and design, p.234-237, July 25-27, 2000, Rapallo, Italy
	Alex Jones , Debabrata Bagchi , Satrajit Pal , Xiaoyong Tang , Alok Choudhary , Prith Banerjee, PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
	H. Kojima , A. Shridhar, Interlaced accumulation programming for low power DSP, Proceedings of the 1996 international symposium on Low power electronics and design, p.213-216, August 12-14, 1996, Monterey, California, United States
	E. Musoll , J. Cortadella, Scheduling and resource binding for low power, Proceedings of the 8th international symposium on System synthesis, p.104-109, September 13-15, 1995, Cannes, France
	Daehong Kim , Kiyoung Choi, Power-conscious high level synthesis using loop folding, Proceedings of the 34th annual conference on Design automation, p.441-445, June 09-13, 1997, Anaheim, California, United States
	Daehong Kim , Dongwan Shin , Kiyoung Choi, Low power pipelining of linear systems: a common operand centric approach, Proceedings of the 2001 international symposium on Low power electronics and design, p.225-230, August 2001, Huntington Beach, California, United States
	Junghwan Choi , Jinhwan Jeon , Kiyoung Choi, Power minimization of functional units partially guarded computation, Proceedings of the 2000 international symposium on Low power electronics and design, p.131-136, July 25-27, 2000, Rapallo, Italy
	Anand Raghunathan , Sujit Dey , Niraj K. Jha , Kazutoshi Wakabayashi, Power management techniques for control-flow intensive designs, Proceedings of the 34th annual conference on Design automation, p.429-434, June 09-13, 1997, Anaheim, California, United States
	Ganesh Lakshminarayana , Anand Raghunathan , Niraj K. Jha , Sujit Dey, Transforming control-flow intensive designs to facilitate power management, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.657-664, November 08-12, 1998, San Jose, California, United States
	Preeti Ranjan Panda , Lakshmikantam Chitturi, An energy-conscious algorithm for memory port allocation, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.572-576, November 10-14, 2002, San Jose, California
	Konstantinos Masselos , Panagiotis Merakos , Spyros Theoharis , Thanos Stouraitis , Costas E. Goutis, Power efficient data path synthesis of sum-of-products computations, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.446-450, June 2003
	Kimiyoshi Usami , Mutsunori Igarashi, Low-power design methodology and applications utilizing dual supply voltages, Proceedings of the 2000 conference on Asia South Pacific design automation, p.123-128, January 2000, Yokohama, Japan
	Ahmed F. Shalash , Keshab K. Parhi, Power Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications, Journal of VLSI Signal Processing Systems, v.25 n.3, p.199-213, July 2000
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	Lin Zhong , Niraj K. Jha, Interconnect-aware high-level synthesis for low power, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.110-117, November 10-14, 2002, San Jose, California
	Zili Shao , Qingfeng Zhuge , Meilin Liu , Chun Xue , Edwin H. M. Sha , Bin Xiao, Algorithms and analysis of scheduling for loops with minimum switching, International Journal of Computational Science and Engineering, v.2 n.1/2, p.88-97, June 2006
	Alex K. Jones , Raymond Hoare , Dara Kusic , Gayatri Mehta , Josh Fazekas , John Foster, Reducing power while increasing performance with supercisc, ACM Transactions on Embedded Computing Systems (TECS), v.5 n.3, p.658-686, August 2006
	Enric Musoll , Jordi Cortadella, Register-Transfer Level Transformations for Low-Power Data-Paths, Integrated Computer-Aided Engineering, v.5 n.4, p.315-332, December 1998
	Gerd Jochens , Lars Kruse , Eike Schmidt , Wolfgang Nebel, A new parameterizable power macro-model for datapath components, Proceedings of the conference on Design, automation and test in Europe, p.8-es, January 1999, Munich, Germany
	J. E. Crenshaw , M. Sarrafzadeh, Accurate high level datapath power estimation, Proceedings of the 1997 European conference on Design and Test, p.590, March 17-20, 1997
	Lih-Yih Chiou , Swarup Bhunia , Kaushik Roy, Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications, Proceedings of the conference on Design, Automation and Test in Europe, p.10096, March 03-07, 2003
	L. Benini , P. Vuillod , G. de Micheli , Claudionor Coelho, Synthesis of low-power selectively-clocked systems from high-level specification, Proceedings of the 9th international symposium on System synthesis, p.57, November 06-08, 1996
	Meikang Qiu , Meiqin Liu , Hao Li , Hung-Chung Huang , Wenyuan Li , Jiande Wu, Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture, Journal of Signal Processing Systems, v.57 n.3, p.363-379, December 2009