Towards a high-level power estimation capability

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Towards a high-level power estimation capability

Full text

Pdf (206 KB)

Source

International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 87 - 92

Year of Publication: 1995

ISBN:0-89791-744-8

Author

Farid N. Najm

ECE Dept. and Coordinated Science Lab., University of Illinois at Urbana-Champaign, Urbana, IL

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 14, Citation Count: 16

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/224081.224097 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Farid N. Najm, A survey of power estimation techniques in VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.446-455, Dec. 1994 [doi>10.1109/92.335013]
	2	L. Hellerman, "A measure of computational work," IEEE Transactions on Computers, vol. C-21, no. 5, pp. 439-446, May 1972.
	3	K. Mase, "Comments on "A measure of computation work" and "Logical network cost and entropy," IEEE Transactions on Computers, vol. C-27, no. 1, pp. 94-95, January 1978.
	4	R. W. Cook, and M. J. Flynn, "Logical network cost and entropy," IEEE Transactions on Computers, vol. C-22, no. 9, pp. 823-826, September 1973.
	5	N. Pippenger, "Information theory and the complexity of Boolean functions," Mathematical Systems Theory, vol. 10, New York: Springer-Verlag Inc., pp. 129-167, 1977.
	6	J. A. Dussault, "A testability measure," IEEE Digital Semiconductor Test Symposium, Cherry Hill, N J, pp. 113- 116, Oct-Nov. 1978.
	7	V. D. Agrawal, "Information theory in digital testing - a new approach to functional test pattern generation," IEEE International Conference on Circuits and Computers, Port Chester, NY, pp. 928-931, Oct. 1-3, 1980.
	8	Kwang-Ting Cheng , Vishwani D. Agrawal, An entropy measure for the complexity of multi-output Boolean functions, Proceedings of the 27th ACM/IEEE conference on Design automation, p.302-305, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123282]
	9	Thomas M. Cover , Joy A. Thomas, Elements of information theory, Wiley-Interscience, New York, NY, 1991
	10	F. Najm, "Transition density : a new measure of activity in digital circuits," IEEE Transactions on Computer-Aided Design, vol. 12, no. 2, pp. 310-323, February 1993.
	11	Farid N. Najm , Shashank Goel , Ibrahim N. Hajj, Power estimation in sequential circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.635-640, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217602]
	12	Shimon Even, Graph Algorithms, W. H. Freeman & Co., New York, NY, 1979
	13	José Monteiro , Srinivas Devadas , Bill Lin, A methodology for efficient estimation of switching activity in sequential logic circuits, Proceedings of the 31st annual conference on Design automation, p.12-17, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196252]
	14	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Exact and approximate methods for calculating signal and transition probabilities in FSMs, Proceedings of the 31st annual conference on Design automation, p.18-23, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196255]
	15	F. Najm, "Statistical Estimation of the Signal Probability in VLSI Circuits," Coordinated Science Laboratory Report ~UILU-ENG-93-2211, April 1993.
	16	Michael G. Xakellis , Farid N. Najm, Statistical estimation of the switching activity in digital circuits, Proceedings of the 31st annual conference on Design automation, p.728-733, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196628]

CITED BY 16

	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Kamal S. Khouri , Ganesh Lakshminarayana , Niraj K. Jha, Fast high-level power estimation for control-flow intensive design, Proceedings of the 1998 international symposium on Low power electronics and design, p.299-304, August 10-12, 1998, Monterey, California, United States
	Weidong Wang , Anand Raghunathan , Ganesh Lakshminarayana , Niraj K. Jha, Input space adaptive design: a high-level methodology for energy and performance optimization, Proceedings of the 38th conference on Design automation, p.738-743, June 2001, Las Vegas, Nevada, United States
	Farid N. Najm, Power estimation techniques for integrated circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.492-499, November 05-09, 1995, San Jose, California, United States
	E. Musoll , J. Cortadella, Scheduling and resource binding for low power, Proceedings of the 8th international symposium on System synthesis, p.104-109, September 13-15, 1995, Cannes, France
	Mahadevamurty Nemani , Farid N. Najm, High-level area and power estimation for VLSI circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.114-119, November 09-13, 1997, San Jose, California, United States
	M. Nemani , F. Najm, High-level power estimation and the area complexity of Boolean functions, Proceedings of the 1996 international symposium on Low power electronics and design, p.329-334, August 12-14, 1996, Monterey, California, United States
	M. Stan , W. Burleson, Two dimensional codes for low power, Proceedings of the 1996 international symposium on Low power electronics and design, p.335-340, August 12-14, 1996, Monterey, California, United States
	Paul Landman, High-level power estimation, Proceedings of the 1996 international symposium on Low power electronics and design, p.29-35, August 12-14, 1996, Monterey, California, United States
	N. Shanbhag, Lower bounds on power dissipation for DSP algorithms, Proceedings of the 1996 international symposium on Low power electronics and design, p.43-48, August 12-14, 1996, Monterey, California, United States
	Anand Raghunathan , Sujit Dey , Niraj K. Jha, Register-transfer level estimation techniques for switching activity and power consumption, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.158-165, November 10-14, 1996, San Jose, California, United States
	Anand Raghunathan , Sujit Dey , Niraj K. Jha, High-level macro-modeling and estimation techniques for switching activity and power consumption, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.538-557, August 2003
	Weidong Wang , Anand Raghunathan , Ganesh Lakshminarayana , Niraj K. Jha, Input space adaptive design: a high-level methodology for optimizing energy and performance, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.6, p.590-602, June 2004
	D. T. Blaauw , A. Dharchoudhury , R. Panda , S. Sirichotiyakul , C. Oh , T. Edwards, Emerging power management tools for processor design, Proceedings of the 1998 international symposium on Low power electronics and design, p.143-148, August 10-12, 1998, Monterey, California, United States
	Prashant Agrawal , Srinivasa R. STG , Ajit N. Oke , Saurabh Vijay, A path based modeling approach for dynamic power estimation, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Weidong Wang , Anand Raghunathan , Ganesh Lakshminarayana , Niraj K. Jha, Input Space Adaptive Embedded Software Synthesis, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.711, January 07-11, 2002