Transformation and synthesis of FSMs for low-power gated-clock implementation

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Transformation and synthesis of FSMs for low-power gated-clock implementation

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 21 - 26

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

Luca Benini	Center for Integrated Systems, Stanford University, Stanford, CA
Giovanni De Micheli	Center for Integrated Systems, Stanford University, Stanford, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 30, Citation Count: 12

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	L. Benini, P. Siegel and G. De Micheli, "Automatic synthesis of gated clocks for power reduction in sequential circuits" IEEE Design and Test of Computers, pp. 32-40, Dic. 1994.
	3	Amelia Shen , Abhijit Ghosh , Srinivas Devadas , Kurt Keutzer, On average power dissipation and random pattern testability of CMOS combinational logic networks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.402-407, November 1992, Santa Clara, California, United States
	4	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Technology decomposition and mapping targeting low power dissipation, Proceedings of the 30th international conference on Design automation, p.68-73, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164577]
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	14	Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education, 1994
	15	O. Coudert , J. C. Madre, Implicit and incremental computation of primes and essential primes of Boolean functions, Proceedings of the 29th ACM/IEEE conference on Design automation, p.36-39, June 08-12, 1992, Anaheim, California, United States
	16	Radu Marculescu , Diana Marculescu , Massoud Pedram, Switching activity analysis considering spatiotemporal correlations, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.294-299, November 06-10, 1994, San Jose, California, United States
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CITED BY 12

	Sue-Hong Chow , Yi-Cheng Ho , TingTing Hwang , C. L. Liu, Low power realization of finite state machines—a decomposition approach, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.3, p.315-340, July 1996
	Xunwei Wu , Jian Wei , Massoud Pedram , Qing Wu, Low-power design of sequential circuits using a quasi-synchronous derived clock, Proceedings of the 2000 conference on Asia South Pacific design automation, p.345-350, January 2000, Yokohama, Japan
	José C. Monteiro , Arlindo L. Oliveira, FSM decomposition by direct circuit manipulation applied to low power design, Proceedings of the 2000 conference on Asia South Pacific design automation, p.351-358, January 2000, Yokohama, Japan
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Srinivas Devadas , Sharad Malik, A survey of optimization techniques targeting low power VLSI circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.242-247, June 12-16, 1995, San Francisco, California, United States
	Xunwei Wu , Massoud Pedram, Low power sequential circuit design by using priority encoding and clock gating, Proceedings of the 2000 international symposium on Low power electronics and design, p.143-148, July 25-27, 2000, Rapallo, Italy
	Jerry Frenkil, Issues and directions in low power design tools: an industrial perspective, Proceedings of the 1997 international symposium on Low power electronics and design, p.152-157, August 18-20, 1997, Monterey, California, United States
	Saurabh Chaudhury , Krishna Teja Sistla , Santanu Chattopadhyay, Genetic algorithm-based FSM synthesis with area-power trade-offs, Integration, the VLSI Journal, v.42 n.3, p.376-384, June, 2009
	Hirofumi Iwato , Keishi Sakanushi , Yoshinori Takeuchi , Masaharu Imai, A low power VLIW processor generation method by means of extracting non-redundant activation conditions, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, September 30-October 03, 2007, Salzburg, Austria
	P. Surti , L. F. Chao , A. Tyagi, Low power FSM design using Huffman-style encoding, Proceedings of the 1997 European conference on Design and Test, p.521, March 17-20, 1997
	M. Favalli , L. Benini , G. de Micheli, Design for Testability of Gated-Clock FSMs, Proceedings of the 1996 European conference on Design and Test, p.589, March 11-14, 1996
	L. Benini , P. Vuillod , G. de Micheli , Claudionor Coelho, Synthesis of low-power selectively-clocked systems from high-level specification, Proceedings of the 9th international symposium on System synthesis, p.57, November 06-08, 1996