Variable voltage scheduling

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Variable voltage scheduling

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 9 - 14

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

Salil Raje	Northwestern University, Electrical and Computer Science, Evanston, IL
Majid Sarrafzadeh	Northwestern University, Electrical and Computer Science, Evanston, IL

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 46, Citation Count: 54

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	L. S. Nielsen and J. Sparso, "Low-Power Operation Using Self-Timed Circuits and Adaptive Scaling of the Supply Voltage", Proc. of the International Workshop on Low Power Design, April 1994, pp. 99-104.
	2	Lars S. Nielsen , Cees Niessen, Low-power operation using self-timed circuits and adaptive scaling of the supply voltage, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.391-397, Dec. 1994 [doi>10.1109/92.335008]
	3	A. Chandrakasan, S. Sheng, and R. Brodersen," Lowpower CMOS Digital Design", IEEE Journal of Solidstate circuit, April 1992, pp. 473-484.
	4	José Monteiro , Srinivas Devadas , Abhijit Ghosh, Retiming sequential circuits for low power, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.398-402, November 07-11, 1993, Santa Clara, California, United States
	5	Mazhar Alidina , José Monteiro , Srinivas Devadas , Abhijit Ghosh , Marios Papaefthymiou, Precomputation-based sequential logic optimization for low power, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.426-436, Dec. 1994 [doi>10.1109/92.335011]
	6	Kaushik Roy , Sharat Prasad, SYCLOP: Synthesis of CMOS Logic for Low Power Applications, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.464-467, October 11-14, 1992
	7	R. A. Walker and R. Camposano, "A Survey of High- Level Synthesis Systems". Kluwer, MA, 1991.
	8	A. P. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. W. Brodersen, "Optimizing Power Using Transformations", Transcript of the journal paper (not yet published).

CITED BY 54

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	Inki Hong , Darko Kirovski , Gang Qu , Miodrag Potkonjak , Mani B. Srivastava, Power optimization of variable voltage core-based systems, Proceedings of the 35th annual conference on Design automation, p.176-181, June 15-19, 1998, San Francisco, California, United States
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Chingwei Yeh , Yin-Shuin Kang , Shan-Jih Shieh , Jinn-Shyan Wang, Layout techniques supporting the use of dual supply voltages for cell-based designs, Proceedings of the 36th ACM/IEEE conference on Design automation, p.62-67, June 21-25, 1999, New Orleans, Louisiana, United States
	Chi-Hong Hwang , Allen C.-H. Wu, A predictive system shutdown method for energy saving of event-driven computation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.226-241, April 2000
	Chunhong Chen , Majid Sarrafzadeh, Power reduction by simultaneous voltage scaling and gate sizing, Proceedings of the 2000 conference on Asia South Pacific design automation, p.333-338, January 2000, Yokohama, Japan
	J. Chang , M. Pedram, Energy minimization using multiple supply voltages, Proceedings of the 1996 international symposium on Low power electronics and design, p.157-162, August 12-14, 1996, Monterey, California, United States
	Vijay Sundararajan , Keshab K. Parhi, Synthesis of low power CMOS VLSI circuits using dual supply voltages, Proceedings of the 36th ACM/IEEE conference on Design automation, p.72-75, June 21-25, 1999, New Orleans, Louisiana, United States
	Tohru Ishihara , Hiroto Yasuura, Voltage scheduling problem for dynamically variable voltage processors, Proceedings of the 1998 international symposium on Low power electronics and design, p.197-202, August 10-12, 1998, Monterey, California, United States
	Chunhong Chen , Ankur Srivastava , Majid Sarrafzadeh, On gate level power optimization using dual-supply voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.5, p.616-629, October 2001
	Chingwei Yeh , Min-Cheng Chang , Shih-Chieh Chang , Wen-Bone Jone, Gate-level design exploiting dual supply voltages for power-driven applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.68-71, June 21-25, 1999, New Orleans, Louisiana, United States
	De-Sheng Chen , Majid Sarrafzadeh, An exact algorithm for low power library-specific gate re-sizing, Proceedings of the 33rd annual conference on Design automation, p.783-788, June 03-07, 1996, Las Vegas, Nevada, United States
	Ki-Seok Chung , Taewhan Kim , C. I. Liu, Behavioral-level partitioning for low power design in control-dominated application, Proceedings of the 10th Great Lakes symposium on VLSI, p.156-161, March 02-04, 2000, Chicago, Illinois, United States
	Chingwei Yeh , Yin-Shuin Kang, Cell-based layout techniques supporting gate-level voltage scaling for low power, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.983-986, 12/1/2001
	Abram Dancy , Anantha Chandrakasan, A reconfigurable dual output low power digital PWM power converter, Proceedings of the 1998 international symposium on Low power electronics and design, p.191-196, August 10-12, 1998, Monterey, California, United States
	Chunhong Chen , Majid Sarrafzadeh, Provably good algorithm for low power consumption with dual supply voltages, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.76-79, November 07-11, 1999, San Jose, California, United States
	Woo-Cheol Kwon , Taewhan Kim, Optimal voltage allocation techniques for dynamically variable voltage processors, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Yann-Rue Lin , Cheng-Tsung Hwang , Allen C.-H. Wu, Scheduling techniques for variable voltage low power designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.2, p.81-97, April 1997
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	Amitabh Menon , S. K. Nandy , Mahesh Mehendale, Multivoltage scheduling with voltage-partitioned variable storage, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
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	Deming Chen , Jason Cong , Fei Li , Lei He, Low-power technology mapping for FPGA architectures with dual supply voltages, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Enrico Macii , Massoud Pedram , Fabio Somenzi, High-level power modeling, estimation, and optimization, Proceedings of the 34th annual conference on Design automation, p.504-511, June 09-13, 1997, Anaheim, California, United States
	Paul Lukowicz , Urs Anliker , Gerhard Tröster , Steven J. Schwartz , Richard W. DeVaul, The WearARM Modular, Low-Power Computing Core, IEEE Micro, v.21 n.3, p.16-28, May 2001
	Inki Hong , Miodrag Potkonjak , Mani B. Srivastava, On-line scheduling of hard real-time tasks on variable voltage processor, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.653-656, November 08-12, 1998, San Jose, California, United States
	Hsueh-Chih Yang , Lan-Rong Dung, On multiple-voltage high-level synthesis using algorithmic transformations, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Chunhong Chen, Physical design with multiple on-chip voltages, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Gang Qu, What is the limit of energy saving by dynamic voltage scaling?, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Deming Chen , Jason Cong, Delay optimal low-power circuit clustering for FPGAs with dual supply voltages, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Shaoxiong Hua , Gang Qu, Energy-efficient dual-voltage soft real-time system with (m,k)-firm deadline guarantee, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
	Woo-Cheol Kwon , Taewhan Kim, Optimal voltage allocation techniques for dynamically variable voltage processors, ACM Transactions on Embedded Computing Systems (TECS), v.4 n.1, p.211-230, February 2005
	Mikhail Popovich , Eby G. Friedman , Michael Sotman , Avinoam Kolodny, On-chip power distribution grids with multiple supply voltages for high performance integrated circuits, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
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	J. E. Crenshaw , M. Sarrafzadeh, Accurate high level datapath power estimation, Proceedings of the 1997 European conference on Design and Test, p.590, March 17-20, 1997
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